This paper presents the design and applications of the Open-Source Circuit Radiation Effects (OSCRE) simulation framework. The framework addresses the challenges of simulating radiation effects in integrated circuits by providing a custom library of SPICE-compatible radiation simulation cells and a user-friendly interface based on open-source EDA tools. The radiation library can be easily configured by the circuit designer to model different behaviors of single-event effects (SEE) in a circuit, including double exponential, dual double exponential, and adaptive double exponential effects. We demonstrate the effectiveness and utility of OSCRE to simulate radiation effects in two example circuits: an SRAM cell and an op amp.

Reservoir computing (RC) significantly reduces the requirement on hardware and training resources, making it suitable for edge-computing applications. This work proposes using voltage-controlled oscillator (VCO)-based spiking neurons for RC to leverage the intrinsic randomness and variability of the neuron circuit for low-power operations. We describe the underlying circuit design and propose a network architecture based on the spiking neuron for RC. We demonstrate the effectiveness of the proposed RC network using VCO-based spiking neurons through benchmark tasks and electrocardiogram (ECG) classification.

Hybrid photonic-electronic circuits involving crossdomain feedback signals are difficult to validate and troubleshoot. This paper describes an approach to model and validate an offset-cancellation loop for a hybrid transimpedance amplifier (TIA) using all-electronic circuits. An equivalent electrical model is developed for the tunable interferometer attenuators used for offset trimming, and it includes test features to extract the system performance. The stability analysis of the system shows 75◦of phase margin and 102 dB of gain margin. Measurement results demonstrate good agreement with analysis and successful TIA offset cancellation.

The multi-stage charge pump in a zero-crossing-based amplifier (ZCBA) presents complex trade-offs. In this brief, we propose a generalized behavioral model for the ZCBA to quickly predict the optimal charge pump design for a ZCBA based on circuit parameters, without conducting time-consuming transistor-level simulations iteratively. This model enables us to numerically analyze in MATLAB the effects of the circuit parameters, which include the current scaling factor, number of current sources, current value, and input amplitude, on the settling performance including overshoot and settling time. The analysis results conclude that there exists an optimal number of stages that yields the fastest settling time for a given total current and load capacitance. Additionally, the settling time exhibits an asymptotic behavior with respect to the total current. To validate this behavioral model, we designed and simulated a transistor-level ZCBA in a 28-nm CMOS process, demonstrating a good agreement between the model analysis and simulation result.

Trade-offs in the design of wideband and energy-efficient inverter-based amplifiers (IAs) will be analyzed and compared to the conventional Current-Mode Logic (CML) based circuits. For a proper comparison, the minimum current consumption of generic IA and the CML amplifiers, with and without active-peaking, will be calculated for a set of target Gain-Bandwidth Product (GBWP) values. This study shows that IAs consume not only lower energy and power compared to their CML counterparts for a given speed specification, but also offer a higher maximum achievable operating frequency. Closed-form expressions, with less than 5% mismatch with simulation results, will be provided to analyze speed-power trade-offs in this type of circuit. This study shows that the consumption of IA circuits (with active peaking) can be lowered by a factor of close to two compared to the CML (with active peaking) in CMOS 28 nm technology, while extending the maximum achievable GBWP by about 12%.

Due to its excellent power efficiency, the successive-approximation-register (SAR) analog-to-digital converter (ADC) is an attractive design choice for low-power ADC implements. In analog layout design, the parasitics induced by interconnecting wires and elements affect the accuracy and performance of the device. Due to the requirement of low-power and high-speed, series of very small lateral metal-metal capacitor units are usually adopted as the architecture of capacitor array. Besides power consumption and area reduction, the parasitic capacitance would significantly affect the matching properties and settling time of capacitors. This work presents a framework to synthesize good-quality binary-weighted capacitors for custom SAR ADC. Also, this work proposes a parasitic-aware ILP-based weight-dynamic network routing algorithm to generate a layout considering parasitic capacitance and capacitance ratio mismatch simultaneously. The experimental result shows that the effective number of bits (ENOB) of the layout generated by our approach is comparable to or better than that of manual design and other automated works, closing the gap between pre-sim and post-sim results.

This paper describes a 10-bit 5-kHz SAR ADC under an ultra-low-supply-voltage of 0.2 V for low-power applications. To tolerate the severe variations in the subthreshold regime, a novel dynamic bulk biasing circuit senses the NMOS/PMOS strength ratio in the background and applies feedback to equalize the strengths to maintain the circuit functionality. A rigorous analysis examines the dynamics and convergence of the proposed biasing circuit in the time- and$z$-domains. A new comparator relaxes the stringent speed-noise trade-off under the 0.2-V supply. Employing switched ac-coupling, stacked input pairs, and voltage-boosted load capacitors, the comparator achieves more than a threefold improvement in speed with little noise penalty. The DAC implements grouped capacitors with quantized sub-radix-2 scaling for redundancy and low power and achieves 10-bit matching. Details of the complete ADC design are described. The measured ADC consumes 22 nW and exhibits a peak DNL and INL of 0.45 LSB and 0.67 LSB, respectively. The measured SFDR and SNDR at Nyquist are 70.6 dB and 52.8 dB, respectivley, yielding an FoM of 12.3 fJ/conv.-step. Measurements show the dynamic bulk biasing compensates the N/P strength ratio variations to optimize the SNDR. We also show that the proposed dynamic bulk biasing successfully maintains the ADC performance over supply variations and improves the yield by nearly twofold over 20 chips.

A charge amplifier incorporates digital circuits as an alternative to the classic analog amplifier to achieve a high open-loop gain to maintain a consistent closed-loop gain over input capacitance variations. The digital-assisted charge amplifier employs a comparator, digital control logic, differential charge pump, current sources, common-mode feedback, and clock generator. A detailed analysis studies the amplifier stability and trade-off between ripple voltage and settling speed. A novel two-step reset scheme and tri-state charge pump minimize the output offset due to ripple residues. Fabricated in a 180-nm CMOS process, the digital-assisted amplifier achieves an open-loop gain of 101 dB, closed-loop gain of$15.0~\mu \text{V}$/e-, input-referred noise of 221$\text{e}^{-}$rms, and output swing of 3 V while consuming 2.19 mW. The amplifier also demonstrates the ability to amplify a dynamic input current using a custom opto-electronic test setup. The amplifier maintains a consistent closed-loop gain across parasitic input capacitance from 6 pF to 94 pF.

A detector connected to a charge amplifier adds parasitic input capacitance that alters the amplifier's gain. The detector capacitance therefore must be characterized so as to properly account for its effect. This paper presents a novel, compact technique to measure the detector capacitance by exploiting the circuit elements within the charge amplifier itself. Reconfiguring the charge amplifier with programmable switches, a capacitor divider network emerges to measure the detector capacitance without the need for any accurate timing references and complex controls. Experimental results of the proposed charge amplifier fabricated in a 180-nm CMOS technology demonstrate the ability to measure the detector capacitance to within 3% of its actual value. An actual charge measurement is also presented.