Trends in image sensor design increasingly demand high resolution, small pixel pitch, low power consumption, and high dynamic range. Digital pixel sensors, in which each pixel directly produces a digital output, are an emerging technology capable of meeting these requirements, with the potential to incorporate in-array image post-processing. This paper presents an implementation for infrared readout circuits based on pulse-frequency modulation. A non-uniform time-based second conversion stage featuring an input-dependent resolution selection enhances dynamic range without increasing pixel area. The effects of key design variables are analyzed, and design guidelines are provided for optimizing system performance. A prototype chip with pixel-parallel conversion in a$10~{\mu }$m pixel pitch is developed following these guidelines, and mathematical simulations validate the effectiveness of the proposed methodology. Finally, even if this work focuses on infrared readout, the design guidelines provided in this work applies and can be extended to any current-sensing system.

This paper presents a system-level solution to correct the jitter noise originating from the phase-locked loop (PLL) in transceiver systems. The solution circumvents the traditional power-noise trade-off present when optimizing the phase noise within a PLL, which quickly dominates the system power for high-speed communication. It reduces the power scaling from a fourth-order dependence on system precision down to a second-order scaling. A digital jitter correction method is proposed that uses a reference sinusoid provided by the transmitter to measure and correct jitter errors, allowing the reference itself to be noisy. Only a limited overhead in system bandwidth and dynamic range is required for the reference. A digital signal processor (DSP) performs the post-processing on the received data and can be inserted into existing analog-to-digital converter (ADC) based communication systems. The proposed jitter correction method is experimentally validated by means of a prototype PCB with off-the-shelf components using a 39-MS/s ADC with 75.5 psRMSof jitter on its clock. An improvement of 10.5 dB in the signal-to-noise ratio (SNR) in the jitter-dominated region is observed, at the cost of only a 15% reduction of the system bandwidth and 1/9th of the input swing of the receiver PCB.

This article presents a fully dynamic latched comparator with a high-gain three-stage configuration and an extra parallel feed-forward path, able to achieve a delay of 26.8 ps and a data rate of 13.5 Gb/s with less than 10−12 BER for a 5$\text{m}\text {V}_{\text {pp}}$differential input ($\Delta V_{\textrm {I}}$) at 0.5 V common-mode ($V_{\textrm {CM}}$) and 1V supply ($V_{\textrm {DD}}$). Additionally, the reduced-stacking cascaded triple-latch arrangement enables a$V_{\textrm {DD}}$. The comparator is analyzed and compared against two prior art circuits by means of derived delay and noise expressions, serving as design guidelines. The prototype comparator and its prior art are fabricated in 28 nm bulk CMOS, with delay, input-referred noise, energy/comparison, and area measurements highlighting the benefits and trade-offs of the proposed solution.

This paper presents a low-power 10-Gb/s vertical cavity surface emitting laser (VCSEL) driver integrated circuit (IC) with electrostatic discharge (ESD) protection in the 130-nm CMOS technology. A distributed amplifier (DA)-based modulator is proposed to boost the driver bandwidth. It employs artificial transmission lines to cancel the device parasitic capacitances of the driver. A distributed ESD protection technique is applied to equalize the group delay of the DA to optimize the jitter performance. To minimize the silicon area, the optimal number of DA taps in the proposed modulator has been derived. To compensate for the capacitive load and the channel losses at the output of the driver, a frequency-domain preemphasis scheme is proposed. The proposed DA modulator occupies an area of 0.69 mm2, and the entire driver IC has a die size of 2 mm×2 mm, including the pads. Both electrical and optical tests have been carried out to characterize the performance of the proposed VCSEL driver IC. Measurements at a data rate of 10-Gb/s demonstrate a typical power consumption of 85 mW under a single 2.5 V supply voltage (49 mW, if separate 1.2 and 2.5 V supplies are used) and an rms jitter of 0.63 and 1.12 ps for the electrical test and optical test, respectively.