Accurate analytic models for the area, delay and power of the Hypermesh NoC topology, realized with the Altera family of FPGAs, are presented. Hypermeshes are based on the concept of hypergraphs, which consist of a set of nodes and a set of hyperedges, where the hyperedges represent low-latency switches which interconnect multiple nodes with deterministic latencies. Three different switch designs for the hyperedges are proposed and evaluated. Two parallel algorithms are considered; (a) the Bitonic sorting algorithm, and (b) the FFT parallel algorithm. The analytic models are shown to be very accurate, typically within 6 percent. The 2D Hypermesh is compared to the 2D layouts of the binary hypercubes (BHC) and generalized hypercubes (GHC) in terms of area, energy per algorithm, and theEnergy-Area product. TheEnergy-Area productis proposed as an useful design metric to evaluate NoCs, which combines both thecostand theperformancemetrics of an NoC into one. Our analysis indicates that the 2D Hypermeshes generally have considerably lower area, energy, andEnergy-Area productcompared to the 2D layouts of the Hypercubes.

We present experimental results for performance of the 2D hypermesh NoC topology, realized with the Altera Family of FPGAs. Hypermeshes are based on the concept of hypergraphs, which consist of a set of nodes and a set of hyper-edges, where the hyper-edges represent low-latency distributed switches. In a 2D hypermesh, the nodes in each row or column are members of a hyperedge, where packets can traverse a hyperedge without encountering router queuing delays. A comparison of the 2D hypermesh, the 2D mesh, and hypercube NoCs is presented. Extensive experimental results show that under the constraint of comparable bisection bandwidth, the 2D hypermesh outperforms the other graph-based network topologies.