TDMS Test Scheduler is a novel and user-friendly toolkit for engineers, researchers and instructors that are activated in the field of manufacturing test. It is the first toolkit that supports test scheduling based on Time Division Multiplexing (TDM) for multi-core, multi-VddSystems-on-Chip (SoCs), as far as the author knows. It is able to provide with solutions that minimize test cost, while power and thermal constraints are met. It offers a) a high-level language to facilitate the representation of a test process, b) two efficient solvers exploiting TDM, c) a rich visualization environment, d) a testbed for educational and research activities. It is free to use.

Through-silicon vias (TSVs) are used as high-speed vertical interconnects between dies in a 3-D system-on-a-chip (SoC). However, their speed cannot be exploited during test application due to inherent limitations of the scan-chains of the cores, which prevent the use of high shift frequencies during the scan-in/out operations. Moreover, due to their high area cost, only a limited number of TSVs can be utilized for test application. As a result, TSVs become the bottleneck for transferring the large volume of test-data to the various layers of the stack, and the time for testing the 3-D chip increases a lot. In this paper, we propose an efficient test-access mechanism (TAM) architecture that exploits the high speed of TSVs to minimize the time for testing 3-D SoCs. The proposed TAM architecture is based on a 2-D time-division-multiplexing approach, and by the means of a very effective test-scheduling method, it offers significant savings in test-time, TSV-count and TAM-cost under power and thermal constraints. Extensive experiments on two 3-D benchmark SoCs show the benefits of the proposed method.

The thermal activity during testing can be considerably reduced by applying power-oriented filling of the unspecified bits of test vectors. However, traditional power-oriented X-fill methods do not correlate the thermal activity with delay failures, and they consume all the unspecified bits to reduce the power dissipation at every region of the core. Therefore, they adversely affect the un-modeled defect coverage of the generated test vectors. The proposed method identifies the unspecified bits that are more critical for delay failures, and it fills them in such a way as to create a thermal-safe neighborhood around the most critical regions of the core. For the rest of the unspecified bits a probabilistic model based on output deviations is adopted to increase the un-modeled defect coverage of the test vectors.

The use of multiple voltage levels introduces new challenges for testing multi-Vddsystems-on-chip (SoCs). Timedivision-multiplexing (TDM) tackles many of these challenges and offers very effective test-schedules. However, the effectiveness of TDM for minimizing test time depends on the test-access-mechanism (TAM) in the SoC. Single-VddTAM optimization techniques consider neither the highly constrained test environment of multi-VddSoCs nor the benefits provided by TDM, therefore they are not suitable for multi-VddSoCs. In this paper, we propose the first TAM optimization technique for multi-VddSoCs. The proposed method exploits unique scheduling opportunities and flexibility offered by TDM, and by the means of a branch-&-bound approach, it quickly identifies the most effective TAM configurations. Experiments using large benchmark SoCs as well as SoCs from industry highlight the benefits of the proposed technique on multi-Vdddesigns, for both single-site and multisite test applications.

Through-silicon vias (TSVs) are used as high-speed interconnects between dies in a 3D System-on-Chip (SoC). However, their speed cannot be utilized during test application due to inherent limitations of the scan chains of the cores, which prevent the use of high shift frequencies. Moreover, due to their high area cost, only a limited number of TSVs can be used for test application. As a result, the time needed for transferring test data to the cores in multiple dies can be considerable. We propose an efficient test-access mechanism (TAM) architecture, which exploits the high speed of TSVs to minimize the time for testing 3D SoCs. By the means of time-division multiplexing and an effective test scheduling method, the proposed TAM architecture offers significant savings in test time, TSV count and TAM cost.

In this paper, we present the first TAM optimization technique for multi-VddSoCs. The proposed method exploits unique scheduling opportunities and flexibility offered by TDM, and by the means of a very efficient Branch-&-Bound approach it quickly identifies the most effective TAM configurations. Experiments upon an industrial SoC highlight the benefits of the proposed technique on multi-Vdddesigns.

The use of multiple voltage levels introduces new challenges for testing Multi-VddSoCs. Time-Division-Multiplexing (TDM) tackles many of these challenges and offers very effective test-schedules. However, the effectiveness of TDM for minimizing test time depends on the Test-Access-Mechanism (TAM) in the SoC. Single-VddTAM optimization techniques consider neither the highly constrained test environment of multi-VddSoCs nor the benefits provided by TDM, therefore they are not suitable for multi-VddSoCs. In this paper, we propose the first TAM optimization technique for multi-VddSoCs. The proposed method exploits unique scheduling opportunities and flexibility offered by TDM, and by the means of a Branch-&-Bound approach, it quickly identifies the most effective TAM configurations. Experiments using SoCs from industry highlight the benefits of the proposed technique on multi-Vdddesigns, for both single-site and multi-site test applications.

Dynamic voltage-frequency scaling (DVFS) is used in system-on-chips (SoCs) for power management, but it increases test time because every core must be tested at multiple voltage settings. In addition, testing at lower power supply voltage settings increases the length of each test due to the corresponding reduction in frequencies that can be used for scan shift operations. Existing test scheduling techniques do not consider test applications at multiple voltage settings, therefore they are not effective for reducing test time for DVFS-based SoCs. We propose a time-division multiplexing (TDM) architecture, which uses the highest available frequency for shifting test data into the SoC and then distributes the test data into multiple cores using lower shift frequencies. TDM is accompanied by three test scheduling methods, which are suitable for different scenarios: 1) an integer linear programming-based formulation that offers optimal results for SOCs of moderate size; 2) a greedy approach that provides good results with very short run time even for very large SoCs; and 3) a rectangle-packing approach combined with simulated-annealing that offers a trade-off between run time and test-time reduction for all SoCs. Experimental results on two industrial SoCs highlight the effectiveness of TDM and the associated scheduling methods.

Even though system-on-chip (SoC) testing at multiple voltage settings significantly increases test complexity, the use of a different shift frequency at each voltage setting offers parallelism that can be exploited by time-division multiplexing (TDM) to reduce test length. We show that TDM is especially effective for small-bitwidth and heavily loaded test-access mechanisms (TAMs), thereby tangibly increasing the effectiveness of multi-site testing. However, TDM suffers from some inherent limitations that do not allow the fullest possible exploitation of TAM bandwidth. To overcome these limitations, we propose space-division multiplexing (SDM), which complements TDM and offers higher multi-site test efficiency. We implement space-and time-division multiplexing (STDM) using a new, scalable test-time minimization method based on a combination of bin packing and simulated annealing. Results for industrial SoCs, highlight the advantages of the proposed optimization method.