Demo Data from EDBT 2026 / reviewers in the wild / expert
Philip Ortiz
dblp:144/4733
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2015
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Reconfigurable computing and FPGAs · 50% Hardware accelerators and domain-specific architectures · 25% Processor architecture and microarchitecture · 25% | |
| Databases, data mining, and information retrieval
1 paper |
Data mining · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Hardware accelerators and domain-specific architectures
decision tree classifier |
0.2 | 1 | 2015 | Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF) · IEEE Trans. Computers 2015 |
Reconfigurable computing and FPGAs
FPGA accelerator |
0.2 | 1 | 2015 | Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF) · IEEE Trans. Computers 2015 |
Reconfigurable computing and FPGAs
FPGA implementation |
0.2 | 1 | 2015 | Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF) · IEEE Trans. Computers 2015 |
Processor architecture and microarchitecture › pipelining
pipelined processor |
0.2 | 1 | 2015 | Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF) · IEEE Trans. Computers 2015 |
Data mining › predictive modeling
classification |
0.1 | 1 | 2015 | Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF) · IEEE Trans. Computers 2015 |
Data mining › predictive modeling › classification
decision tree learning |
0.1 | 1 | 2015 | Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF) · IEEE Trans. Computers 2015 |
Methods — techniques the papers use, named apart from their topics
pipelining · 0.4parallel processing · 0.4
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2015 | Pipelined Decision Tree Classification Accelerator Implementation in FPGA (DT-CAIF)abstractDecision tree classification (DTC) is a widely used technique in data mining algorithms known for its high accuracy in forecasting. As technology has progressed and available storage capacity in modern computers increased, the amount of data available to be processed has also increased substantially, resulting in much slower induction and classification times. Many parallel implementations of DTC algorithms have already addressed the issues of reliability and accuracy in the induction process. In the classification process, larger amounts of data require proportionately more execution time, thus hindering the performance of legacy systems. We have devised a pipelined architecture for the implementation of axis parallel binary DTC that dramatically improves the execution time of the algorithm while consuming minimal resources in terms of area. Scalability is achieved when connected to a high-speed communication unit capable of performing data transfers at a rate similar to that of the DTC engine. We propose a hardware accelerated solution composed of parallel processing nodes capable of independently processing data from a streaming source. Each engine processes the data in a pipelined fashion to use resources more efficiently and increase the achievable throughput. The results show that this system is 3.5 times faster than the existing hardware implementation of classification. Fareena Saqib, Aindrik Dutta, James F. Plusquellic, Philip Ortiz, Marios S. Pattichis |
IEEE Trans. Computers | 4 |