Accurately estimating the latency and power consumption of software applications deployed on multicore systems remains a major challenge for early-stage optimization, as existing methods typically rely on slow and resource-intensive simulations.This paper explores modeling application-to-architecture mappings as heterogeneous graphs and investigates Graph Neural Networks (GNNs) for predicting their performance.Four GNN models are evaluated across eleven datasets, considering five neural network-based software applications.The two best models achieve mean absolute percentage errors of about 2% for power prediction and 15% for latency, with prediction times of only a few tens of milliseconds.These results indicate the potential of GNN-based prediction as an efficient alternative to simulation-driven estimation, paving the way for early-stage AI-assisted mapping optimization.

Dynamically reconfigurable architectures allow sharing of hardware resources, which is particularly beneficial for small low-end FPGAs. Based on the online modification of parts of the circuit, these architectures require partial reconfiguration of the chip. Reducing resource availability or usage comes at the cost of a performance penalty affecting execution time. The challenge lies in bitstream management, especially for complex applications that often exceed the internal memory capacity of the FPGA (BRAM). Consequently, the time penalty arises from the need to retrieve partial bitstreams from external memory (e.g., often a DDR) each time it is necessary. Current state-of-the-art reconfiguration controllers are limited to a throughput of 400 MB/s, significantly penalizing reconfiguration times and making dynamic reconfiguration unattractive for real-life applications (e.g., video processing, machine learning applications, and continual and federated learning for embedded systems). This article introduces a novel partial reconfiguration controller architecture that achieves a throughput of up to 1.396 GB/s, a 3.49× acceleration over existing controllers. The reduced reconfiguration time allows the practical use of dynamic reconfiguration with fewer performance penalties. Additionally, the article compares various reconfiguration controllers in terms of time penalties and offers a tradeoff between algorithm complexity, FPGA resources, and performance.

Fast yet accurate performance and timing prediction of complex parallel data flow applications on multi-processor systems remains a difficult discipline. The reason for it comes from the complexity of the data flow applications and the hardware platform with shared resources, like buses and memories. This combination may lead to complex timing interferences that are difficult to express in pure analytical or classical simulation-based approaches. In this work, we propose a message-level communication model for timing and performance prediction of Synchronous Data Flow (SDF) applications on MPSoCs with shared memories. We compare our work against measurement and TLM simulation-based performance prediction models on two case-studies from the computer vision domain. We show that the accuracy and execution time of our simulation outperforms existing approaches and is suitable for a fast yet accurate design space exploration.

Timing prediction of complex parallel data flow applications on multiprocessor systems represents a difficult task due to complex interferences caused by platforms shared resources. In this domain, classical analytical or simulation-based approaches demonstrate scalability issues to deliver fast yet accurate predictions. In this work, we present an experimental evaluation of new simulation-based statistical methods for timing analysis of multiprocessor systems. We adopt a measurement-based approach for the creation of probabilistic system-level models of the studied systems. Efficiency of statistical methods is evaluated for platforms with different levels of complexity from the point of view of shared resources. We compare our approach against measurement and traditional simulation methods on two case-studies from the computer vision domain: a Sobel filter and a JPEG decoder. We show that our simulation approach has good potential for fast yet accurate design space exploration.

Early estimation of performance has become necessary to facilitate design of complex multi-core architectures. Performance evaluation based on extensive simulations is time consuming and needs to be improved to allow exploration of different architectures in acceptable time. In this paper, we propose a method that improves the tradeoff between simulation speed and accuracy in performance models of architectures. This method computes during model execution some of the synchronization instants involved in architecture evolution. It allows grouping and abstracting architecture processes and this way significantly reduces the number of simulation events. Experiments show significant benefits from the computation method on the simulation time. Especially, a simulation speed-up by a factor of 4 is achieved in the considered case study, with no loss of accuracy about estimation of processing resource usage. The proposed method has potential to support automatic generation of efficient architecture models.

The increasing complexity of communication infrastructures in the automotive domain implies the use of reliable models to assist designers in the development process of networked embedded systems. In this context, transaction level modeling, supported by languages as SystemC, is a promising solution to assess performances of networked architectures with a good compromise between accuracy and simulation speed. This article presents the modeling and performance evaluation of a video transmission system supported by three electronic controller units and based on a specific power line communication protocol. The created model incorporates the various communication layers considered. The simulation of the model allows the evaluation of time properties and memory cost inferred.

This article presents the effective implementation of a MC-CDMA modulation scheme. It is shown how the spreading operation and the multi-carrier modulation can be combined in order to carry out computation savings. According to the target component (hardware or software), various structures are proposed. Computation times are also given in the two cases.