This paper presents an energy-efficient low-noise dynamic comparator with a passive charge-pump pre-amplifier (CPP). We demonstrate the effectiveness of a passive pre-amplifier, cascaded to a dynamic comparator, to reduce input referred noise (IRN) of the comparator by a factor of pre-amplifier gain. Furthermore, the passive pre-amplifier, originating from a switched-capacitor amplifier, consumes only switching power, making it less burdensome to add it to the dynamic comparator. The proposed dynamic comparator, designed in a 180-nm CMOS process, achieves 37.1 µV of IRN, 817 fJ of energy per conversion under a 1.2-V supply, and a sampling frequency of 80 kHz. This results in a figure-of-merit of 1.12 nJ·µV2.

This paper presents a galvanic-coupled body channel communication (GC-BCC) transceiver (TRX) system with serpentine-interconnection electrodes for applications in joint replacement surgeries, such as total knee replacement (TKR). The proposed system consists of a GC-BCC transmitter (TX) implanted inside the body and an external receiver (RX). Implanted devices with high stiffness may cause tissue damage or compromise long-term stability due to the inherent curvature and elasticity of the human body. Given these characteristics of the human body, implantable devices should feature flexible and stretchable structures that conform to the body’s contours and minimize such risks. To address this requirement, we propose a serpentine-interconnection electrode pair, which provides mechanical compliance and can replace the conventional straight-interconnection interface. This interconnection enables reliable signal transmission in the MHz band, demonstrating its suitability for both implantable TX and external RX in medical applications. The GC-BCC TX and RX are fabricated using 0.18 µm BCD and 0.18 µm CMOS processes, respectively, achieving a data rate of 20 Mb/s with a bit error rate (BER) of less than 10-6. The TX and RX chips consume an active area of 3.2 mm2and 2.5 mm2and consume a power of 675 µW and 4.32 mW, respectively. The performance of the proposed system is validated through ex-vivo experiments using 10-mm thick porcine tissue.

This paper presents a low input-referred-noise (IRN) discrete-time (DT) delta-sigma modulator (DSM) for precise biopotential-signal acquisition. The proposed structure utilizes a 1st-order input-impedance-boosted kT/C-noise-cancellation integrator combined with a 2nd-order noise-shaping SAR (NS-SAR). The proposed integrator cancels the kT/C noise generated during the sampling and integrating phases by using feedback capacitors for the cancellation loop while boosting the input impedance. This novel integrator can utilize smaller capacitors for sampling and integration than the standard design without any performance degradation. A single amplifier in the integrator is reused for sampling, kT/C noise cancellation, and integration to reduce power consumption. The NS-SAR is utilized instead of an amplifier-based multistage integrator structure to attain high resolution while maintaining low power consumption. The prototype IC, simulated using a 65-nm CMOS process, achieves a 90.5-dB SNDR across a 1-Hz-to-1-kHz bandwidth with a 300-mVPPinput, yielding a 99.8-nV/$\sqrt {{\text{Hz}}} $ IRN and a FoMSNDRof 173.4 dB. These results indicate that the proposed DSM can properly acquire biopotential signals from both muscular and cardiac sources.

This paper presents a time-multiplexed neural recording readout IC (ROIC) for interfacing a high-density microelectrode array (MEA) with integrated switches. Time-domain multiplexing (TDM) allows multiple electrodes to share an analog front-end (AFE) and ADC to save chip area. The design features an input impedance (ZIN) boosting technique using dual positive feedback loops (DPFLs) to cancel internal and external parasitic capacitances across multiple channels using shared DPFL capacitors. Thus, the effective area and number of capacitors to be trimmed for the DPFL technique are also reduced by the multiplexing ratio. The system is implemented in a 180nm CMOS process and uses a chopped capacitively coupled instrumentation amplifier (CCIA) for a fixed gain and low noise, followed by a windowed integration sampling amplifier to reduce the system’s noise equivalent bandwidth and provide programmable gain. The neural recording ROIC occupies an active area of 0.124mm2/ch and consumes 8.81μW/ch. The sampling rate is 20kHz/ch with a simulated input-referred noise of 5.95μVrms from 1Hz to 10kHz. The DPFL capacitors are fully shared across channels and help boost ZINto 840MΩ, demonstrating the effectiveness and suitability of the DPFL ZIN-boosting technique for TDM chopped CCIA AFEs.

This work presents a compact, self-powered pressure sensor based on a triboelectric nanogenerator (TENG), which is developed for total knee replacement (TKR) implants. Unlike conventional bulky and inefficient systems with separate attenuators and signal processing units, this design seamlessly integrates a pressure sensor within an energy-efficient energy harvesting (EH) circuit. The system features a bidirectional, high-voltage (HV) four-input buck converter with a newly proposed HV protector, enhancing EH efficiency across four different input voltages. The converter achieves a maximum end-to-end efficiency of 79.21%. Additionally, the pressure-sensing circuits offer accurate readouts by sampling the HV open-circuit voltages (VOC) from TENGs using a VOCsampler without the need for an attenuator. Compared to state-of-the-art solutions, this work not only achieves competitive energy harvesting performance but also introduces, for the first time, a fully integrated pressure-sensing function.

A hybrid high-voltage regulating charge pump is proposed for point-of-care electrokinetic concentration chip applications. The hybrid charge pump is composed of three cascaded sub-pumps. High efficiency, minimized area, wide output current range, and high regulated output voltage are achieved by selecting charge pump architectures that provide high voltage conversion gain with less number of stages. The proposed charge pump is designed and fabricated in 180 nm BCD process. Simulation results show that the proposed system provides a maximum efficiency of 48.26%, while providing a maximum output voltage of 65 V.

This paper proposes an accelerometer readout integrated circuit (IC) that supports micro-electromechanical systems (MEMS) piezoresistive accelerometers designed for ultrahigh-G measurements. The IC utilizes an adaptive gain path and shock detector to address circuit saturation and settling issues when shock signals are injected. This enables the use of a capacitive coupling structure that mitigates the offsets resulted from sensor mismatches. Additionally, the capacitive coupling allows to employ different supply voltages for the MEMS sensor and the IC. Thus, the IC can use a much lower supply voltage for low power consumption while the MEMS sensor can use a high supply voltage for better output sensitivity. By bypassing a gain stage for lower overall channel gain during the shock signals, the system can ensure the acquisition of accurate signal immediately after the shock signal. The IC was fabricated in 180nm CMOS technology, consuming 1.02 mW from a 1.8V supply voltage. Measurement results show a 85% and 89% enhancement in the common-mode offset and a gain error for a 1-ms shock signal when the proposed adaptive gain is used. The IC with a MEMS piezoresistive accelerometer is also validated by a 50 kG shock survival test.

The measurement of small variation of the bioZ having a substantially large baseline impedance is a great challenge, requiring a wide dynamic range (DR) and a high signal-to-noise ratio (SNR). This paper presents a new impedance measurement architecture based on Δ-ΔΣ modulator with capacitive-feedback baseline cancellation. The readout front-end (RFE) of the integrated circuit (IC) is configured with a first-order Δ-ΔΣ modulator and a feedback capacitive digital-to-analog converter (CDAC) that minimize the power consumption. The front-stage Δ-modulation allows to achieve a wide input DR of 30 kΩ by eliminating the large static baseline impedance with no static current consumption. It also mitigates the input-dependent noise characteristic of the current balancing instrumentation amplifier (CBIA) significantly. The current generator (CG) generates a square wave for the excitation current with a current magnitude ranging from 5 μApkto 100 μApkover a frequency range from 1 kHz to 1024 kHz. The chopping and dynamic element matching (DEM) techniques are adopted in the bandgap reference (BGR), CG, and current-DAC (IDAC) to mitigate their flicker noises, which dominate the signal bandwidth (<10 Hz). The proposed IC designed in a 180-nm CMOS process consumes only 7.64 μW for the I path of the RFE, achieving a maximum SNR of 97.7 dB.

This paper presents a high-throughput impedance readout IC with a novel synchronous cyclic integration technique using a scalable capacitive transimpedance stage. The proposed technique removes the need for the low pass filter (LPF) in the readout chain and performs the I/Q demodulation within a single cycle. Fabricated in a 180-nm CMOS process, the proposed IC consumes 50 μW from a 1.2-V supply. It can measure impedances over a frequency of 100 Hz to 100 kHz with an accuracy of 99.7% and can achieve a throughput of 50 kSps at 100 kHz input frequency.

In this paper, a fully-integrated digital low dropout (DLDO) regulator is proposed utilizing a multi-bits shift handler (MBSH), decremental-gain PMOS array, and adaptive coarse loop controller to achieve fast load transient responses with improved line and load regulations. An undershoot-limiter loop (ULL) is also proposed to help to reduce the voltage undershoot peak during load current transients. To significantly mitigate the steady-state voltage ripples (VRIPP) and quiescent current (IQ), we propose a synchronized fine-loop freezer (FLF) in the fine loop of the DLDO that is only activated when VREGgets equal to VREF. The proposed DLDO was designed and fabricated in a 180-nm CMOS process with an active area of 0.22 mm2. The simulation results demonstrate that the proposed DLDO achieves ≤ 130 μV of VRIPPwhile maintaining a minimum dropout voltage of 20 mV and a peak current efficiency of 99.96 %.

This paper presents a 72-channel resistive-sensor interface integrated circuit (IC). The proposed IC includes 8 sensor oscillators and 8 time-to-digital converters (TDCs), and each set of a sensor oscillator and a TDC is time-multiplexed to measure from 9 sensors. Consequently, it attains impressive energy efficiency of 310 pJ per channel. Employing a time-domain interface approach, the IC directly converts sensor resistance into time, extending its measurement capabilities up to 10 MΩ. It also takes advantage of a high-energy-efficiency phase-locked loop (PLL), resulting in a high signal-to-quantization-noise ratio (SQNR) that reaches the intrinsic signal-to-noise ratio (SNR) of the sensor oscillator. This results in an effective number of bits (ENOB) of 9.3 bits when 310 pJ is consumed for each channel. The ENOB can be adjusted through external FPGA control, and the maximum ENOB achieved is 14.1 with an oversampling ratio (OSR) of 256. The proposed IC, designed and fabricated in a 180-nm CMOS process with an active area of 0.015mm2, consumes only 15.07 μW per channel, resulting in a channel-specific Walden figure of merit (FoM) of 0.48 pJ per conversion step. Furthermore, by adjusting the OSR, the IC achieves an outstanding Schreier FoM of 159.8 dB in scenarios requiring high resolution.

This paper presents a low-noise, low-power biopotential recording IC with programmable gain and a reconfigurable number of channels. The analog front end (AFE) with tunable gain from 20 dB to 54 dB can select the number of channels and combination of channels for reconfigurable signal acquisition capability. The proposed hybrid DC-servo loop is employed for fast electrode DC offset (EDO) cancellation up to 240 mV within 10 ms. Designed in a 0.18-μm CMOS process, the proposed IC achieves input-referred noise (IRN) of 1.12 μVrms at the highest gain mode. The overall system achieves 66.35-dB SNDR with the successive approximation register (SAR) analogto-digital converter (ADC) and consumes 5.74 μW with 0.40 mm2 area per channel.

This paper presents a ΔΣ-modulator-based reconfigurable multimodal sensor interface integrated circuit (IC), offering a novel approach to the multimodal measurement of voltage, capacitive, and current signals. A direct-conversion structure is employed in the multimodal sensor interface, and its reconfigurable ΔΣ modulation scheme ensures compact die area, high energy efficiency, and enhanced dynamic range. Fabricated in a 180-nm CMOS process, the multimodal sensor interface achieves measured dynamic ranges of 70.6 dB, 97.8 dB, and 60.0 dB for voltage, capacitance, and current modes, with measured power consumptions of 22.2 μW, 23.0 μW, and 37.7 μW, respectively. The proposed system demonstrates significant improvements in the dynamic range relative to power consumption compared to other state-of-the-art multimodal sensor interface IC designs.

This paper presents a novel high-throughput impedance measurement integrated circuit (IC) with baseline cancellation for neural EIT applications. The proposed technique uses a peak detector to obtain impedance magnitude every cycle. After taking the peak, the peak detector is reset to a DC baseline voltage. And, the signal swinging between the amplitude and the reset baseline is further amplified, allowing to measure small impedance variations even with a large baseline. The proposed IC fabricated in a 180-nm standard CMOS process can measure impedance variations of >0.1% baseline can be measured, while achieving high throughput of 100 kS/s at 100 kHz input frequency. Scalable design allows the proposed IC to support a wide frequency range from 100 Hz to 100 kHz with a power consumption from 31 μW to 39 μW from a 1.2-V supply.

This paper presents a digital low dropout (DLDO) regulator, which has very small steady-state voltage ripples (VRIPP) ofRIPP, a steady-state control based on a voltage-to-interval converter and a charge pump is proposed. To achieve a fast transient response, a dual-edge-triggered shift registers (DTSR) is used in the coarse loop. In addition, an analog-assisted (AA) loop is proposed to significantly mitigate the voltage undershoot in response to a load current (ILOAD) step. The DLDO was designed and fabricated in a 180-nm CMOS process with an active area of 0.253 mm2. The simulated results demonstrate that the proposed DLDO achieves a line regulation of 8 mV/V and a load regulation of 0.081 mV/mA while driving a maximum ILOADof 75 mA with a peak current efficiency of 99.93 %.

In analog-mixed-signal (AMS) compute-in-memory (CIM) systems, the two’s-complement (2SC) format provides better area efficiency than the sign-and-magnitude (SNM) one. However, the 2SC format exacerbates the challenges of AMS-CIM systems, suffering from significant DNN accuracy drop under process variations and high computation currents from activating multiple WLs. In the 2SC format, ‘0’ and ‘1’ are nearly balanced for all logical-order bits, unlike ‘0’-skewed higher-order bits in the SNM format. Consequently, the 2SC-based AMS-CIM systems have much more on-cells than the SNM-based counterpart, deteriorating the above challenges. We propose Skew-CIM, a software-hardware co-design technique to relax these challenges. Our proposed weight skewing (WESK) breaks the ‘0’ and ‘1’ balance at the software level. The potential accuracy drops resulting from WESK are successfully compensated by retraining DNNs. The offsets caused by WESK can be easily corrected using online hardware-level processing. Our Skew-CIM technique can be applied to most AMS-CIM systems with memories showing large on-off cell current ratios. As an example, we use it in a custom-designed 8T-SRAM-based CIM device, demonstrating a significant reduction in the DNN classification error by 7.6 times compared to the 2SC-based AMS-CIM without our Skew-CIM technique. Furthermore, our Skew-CIM markedly enhances energy efficiency by up to 39.9%, outperforming conventional SNM-based AMS-CIM systems.

We present an energy-efficient, scalable neural stim-ulation IC with adaptive dynamic voltage switching, which can be applied to cochlear implant (CI) systems. The stimulation IC generates three different voltage outputs by operating a single-inductor multiple-output (SIMO) boost converter, while an adaptive dynamic voltage switching (ADVS) block selects an appropriate supply voltage for each stimulation channel among those SIMO outputs. The SIMO boost converter is designed to operate over a wide range of its input, which is the rectifier output of the wirelessly powered CI system. The ADVS control as well as the stimulation amplitude control are performed remotely by an external sound processor (SP) of the CI system in real time. For the ADVS operation, the compliance voltage of each stimulation channel is monitored to be used as an input signal for switching to the appropriate supply voltage for the corresponding stimulation channel. The dynamic voltage switching operation is carried out in sub-us, The stimulation IC with ADVS is implemented using a 180-nm BCD process, and its operation and performance are verified through post-layout simulations. When applying a real audio input using decoded data from a prototype SP, the proposed stimulation IC with ADVS demonstrates 36.6% energy saving compared to the conventional stimulation IC.

This paper presents an impedance-measurement integrated circuit (IC) that extends the input frequency range to 10 MHz at low power consumption. The proposed IC directly measures the magnitude and phase of the target impedance while adopting a reference resistor, which is connected in series with the target impedance, to obviate the nonideal delays that may be introduced by the voltage-controlled current source and the receiver's signal processing paths. On the receiver side of the IC, a frequency shift is performed by a chopper in front of the first-stage instrumentation amplifier (IA). The chopper down- converts the frequency of the incoming signal, which ranges to 10 MHz, to a common intermediate frequency of 10 kHz. As a result, the requirements on the IA bandwidth and the comparator delay are greatly relaxed, leading to a significant power saving. Furthermore, this technique improves the phase accuracy because the time interval corresponding to the phase at a high frequency increases at the down-converted frequency. Finally, the auto-zeroing technique is used to cancel out the comparator offset, thus reducing the magnitude and phase errors. The proposed IC designed in a 180-nm CMOS process consumes only 544 μW for a frequency range from 100 Hz to 10 MHz with the maximum magnitude and phase errors of 1.0% and 1.8°, respectively.

An asynchronous continuous-time level-crossing analog-to-digital converter (LC-ADC) for high-throughput, high-resolution applications is presented. The proposed 10-bit ADC architecture comprises two stages of level-crossing ADCs, the first stage resolving for 5 MSBs and the second folded residue stage for 5 LSBs. Gray encoding of the output bits ensure single-bit transitions between adjacent digital outputs. Compared to uniform-sampling synchronous ADCs, LC-ADCs generate fewer samples for sparse signals, useful in many applications for biomedical signal acquisition, event-driven computer vision, etc. Unlike conventional LC-ADCs with a few comparators tuned for lower power consumption to acquire sparse signals, this two-tier LC-ADC is optimized for high-resolution tracking of continuous signals, like Electrocardiogram (ECG). Designed and fabricated in 0.18-μm CMOS technology, chip area of the proposed ADC is 1310 × 125 μm2. Operating at 1.8 V supply, the ADC consumes 160-426 μW for 1 Hz to 200 kHz input frequencies at full scale amplitude and achieves an energy efficiency figure-of-merit of 4.16-pJ/conv.

Recent demand and initiatives in brain research have driven significant interest toward developing chronically implantable neural interface systems with high spatiotemporal resolution and spatial coverage extending to the whole brain. Electroencephalography-based systems are noninvasive and cost efficient in monitoring neural activity across the brain, but suffer from fundamental limitations in spatiotemporal resolution. On the other hand, neural spike and local field potential (LFP) monitoring with penetrating electrodes offer higher resolution, but are highly invasive and inadequate for long-term use in humans due to unreliability in long-term data recording and risk for infection and inflammation. Alternatively, electrocorticography (ECoG) promises a minimally invasive, chronically implantable neural interface with resolution and spatial coverage capabilities that, with future technology scaling, may meet the needs of recently proposed brain initiatives. In this paper, we discuss the challenges and state-of-the-art technologies that are enabling next-generation fully implantable high-density ECoG interfaces, including details on electrodes, data acquisition front-ends, stimulation drivers, and circuits and antennas for wireless communications and power delivery. Along with state-of-the-art implantable ECoG interface systems, we introduce a modular ECoG system concept based on a fully encapsulated neural interfacing acquisition chip (ENIAC). Multiple ENIACs can be placed across the cortical surface, enabling dense coverage over wide area with high spatiotemporal resolution. The circuit and system level details of ENIAC are presented, along with measurement results.