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Daniel Campello

dblp:145/2083 · DBLP profile ↗
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3ranked-venue papers
1as first author
1since 2021 · last 2022
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 1 since 2021Databases, data management, data science and information retrieval · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Memory systems · 92% Storage systems · 8%
Software engineering, system software, and programming languages
3 papers
Operating systems · 100%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
non-volatile memory
0.722022
MULTI-CLOCK: Dynamic Tiering for Hybrid Memory Systems · HPCA 2022
Software Persistent Memory · USENIX ATC 2012
Memory systems › non-volatile memory
persistent memory
0.722022
MULTI-CLOCK: Dynamic Tiering for Hybrid Memory Systems · HPCA 2022
Software Persistent Memory · USENIX ATC 2012
Memory systems
page placement
0.612022
MULTI-CLOCK: Dynamic Tiering for Hybrid Memory Systems · HPCA 2022
Memory systems
tiered memory
0.612022
MULTI-CLOCK: Dynamic Tiering for Hybrid Memory Systems · HPCA 2022
Storage systems
file systems
0.212015
Non-blocking Writes to Files · FAST 2015
Operating systems › resource management
memory management
0.222022
MULTI-CLOCK: Dynamic Tiering for Hybrid Memory Systems · HPCA 2022
Software Persistent Memory · USENIX ATC 2012
Operating systems › resource management › storage management
file systems
0.112015
Non-blocking Writes to Files · FAST 2015
YearPublicationVenuePosition
2022 MULTI-CLOCK: Dynamic Tiering for Hybrid Memory Systems
abstract
The rapid growth of i-memory computing powered by data-intensive applications has increased demand for DRAM in servers. However, a DRAM-based system can be limiting for modern workloads because of its capacity, cost, and power consumption characteristics. Hybrid memory systems, which consist of different types of memory, such as DRAM and persistent memory, can help address many of these limitations. One promising direction that has been explored in the recent literature involves introducing persistent memory devices as a second memory tier that is directly exposed to the CPU. The resulting tiered memory design must address the fundamental challenge of placing the right data in the right memory tier at the right time while minimizing overhead. We present MULTI -CLOCK, an efficient, low-overhead hybrid memory system that relies on a unique page selection technique for tier placement. MULTl-CLOCK’s page selection captures both page access recency and frequency, and enables moving pages to appropriate tiers at the right time within hybrid memory systems. We implemented a Linux-based, NUMA-aware version of MULTI-CLOCK that is entirely transparent and backward compatible with any existing application. Our evaluation with diverse real-world applications such as graph processing and key-value stores shows that MULTI -CLOCK can improve the average throughput by as much as 352% when compared with several state-of-the-art techniques for tiered memory.
Adnan Maruf, Ashikee Ghosh, Janki Bhimani, Daniel Campello, Andy Rudoff, Raju Rangaswami
HPCA4
2015 Non-blocking Writes to Files
Daniel Campello, Hector López, Ricardo Koller, Raju Rangaswami, Luis Useche
FAST1
2012 Software Persistent Memory
Jorge Guerra, Leonardo Mármol, Daniel Campello, Carlos Crespo, Raju Rangaswami, Jinpeng Wei
USENIX ATC3