This paper proposes a digital background calibration scheme for the compensation of the linear and the third-order nonlinear gain errors of the residue amplifier (RA) in pipelined ADCs. The proposed calibration method, called the piecewise multi-correlation estimation (PMCE) technique, injects two pseudo-random number (PN) sequences within two adjacent dither windows to extract gain coefficients. This method transforms the estimation of nonlinear gains into the estimation of two linear gains, thus achieving rapid convergence. The proposed calibration scheme does not result in the output swing degradation of the multiplying DAC (MDAC) due to dither injection. The required modification to analog circuits involves only three additional comparators and a capacitor for dither injection. Monte Carlo simulation results of a 14-bit 1.3GS/s pipelined ADC show that the average SFDR of the ADC is improved from 59.61 dB to 91.11 dB.

This paper presents a novel parallel convolution-self-attention neural network (PCSANN) based calibration scheme for Pipelined and Pipelined-SAR ADCs. Combining convolution neural network (CNN) and self-attention neural network (SANN), the proposed architecture jointly calibrates various nonlinearities in ADCs as a black box, including comparator offsets, inter-stage gain error (IGE), inter-stage nonlinearity, digital-to-analog converter (DAC) errors, memory effect (ME), etc. This proposed calibration scheme is validated with a fabricated 12-bit 150MSps pipelined ADC prototype and a fabricated 12-bit 750MSps pipelined-SAR ADC prototype. Measurement results show that the spurious-free dynamic range (SFDR) of the pipelined ADC is improved by 14.17dB from 64.98dB to 79.15dB, and the pipelined-SAR ADC achieves a 7.60dB improvement in SFDR from 63.00dB to 70.60dB.

This paper presents a novel calibration scheme for single-channel SAR, pipelined and pipelined-SAR ADCs using Kolmogorov–Arnold networks (KANs). In the proposed scheme, a multi-sample KAN (MS-KAN) is designed to realize nonlinear code synthesis (NLCS), achieving effective calibration for general nonlinear errors. The MS-KAN-based calibrator can be converted into an analytical expression, making the calibration process transparent, with stronger interpretability, predictability and reliability compared to previous neural network-based calibration algorithms, and assisting in the analysis of ADC nonidealities. Meanwhile, the proposed scheme achieves high calibration performance with low hardware overhead. The proposed scheme also requires much fewer training samples, thereby reducing the effort required for both chip testing and network training. The MS-KAN-based calibrator is verified with two silicon-proven ADCs, a 14-bit 1.3 GS/s pipelined ADC and a 10-bit 700MS/s SAR ADC. Measurement results show that SFDR is improved by 11.5 dB to 30.9 dB after calibration. The quantized calibrators are implemented on both FPGA and 28nm CMOS technology, where a piecewise polynomial (PWP) method is adopted to simplify the implementation of the calibrator. The post-layout simulation results show that the calibrator for the real-time calibration of the pipelined ADC consumes only 6.32 mW, while the calibrator for the SAR ADC consumes 2.42 mW.

Calibrating ADCs in the absence of ground truth presents a significant challenge for high-precision applications. This paper addresses this issue by introducing a novel two-step approach that combines evolutionary strategy and deep learning techniques. First, we employ covariance matrix adaptation evolution strategy to obtain ground truth signal samples with optimal SFDR values. This serves as a robust foundation for the subsequent calibration process. Second, we propose a new calibration neural network architecture called controlled residual convolutional neural networks. This architecture introduces a controlled residual branch within the network, allowing for more effective learning and calibration. The controlled residual branch is designed to adaptively adjust the network’s focus between the main and residual paths, thereby enhancing its calibration capabilities. Experimental results underscore the efficacy of our proposed method. Specifically, we observed a 29.01dB improvement in SFDR, representing the maximum enhancement relative to previous methods. These results validate the effectiveness of our approach in achieving high-precision ADC calibration without the need for the information of ground truth signals, thereby making it feasible for background calibration.

This paper proposes a novel digital background calibration technique for interstage gain error (IGE) and gain nonlinearity in pipelined analog-to-digital converters (ADCs). Through the random switching of the multiplying digital-to-analog converter (MDAC) between two operating modes, two interstage residue curves are obtained. The IGE and the third-order gain nonlinearity are calibrated according to the distance and the geometric relationship between the two residue curves, respectively. For the proposed calibration scheme, the analog circuits require no modifications, except for the addition of several multiplexers and switches. The advantages of the proposed technique include a simple algorithm, fast convergence, and low power consumption. The simulation results show that the signal-to-noise and distortion ratio and spurious-free dynamic range of a 14-bit 1 Gsps pipelined ADC improve from 44.86 and 55.54 dB to 77.99 and 86.16 dB, respectively, after calibration. During the calibration process, the IGE and gain nonlinearity converge after 2.5 × 105and 2 × 105sampling cycles, respectively.

This article presents a new artificial neural network (ANN)-based calibration mechanism for analog-to-digital converters (ADCs). The proposed mechanism applies ANN to realize the bijective vector recovery mapping (VRM) for nonlinearity calibration and thus effectively suppresses both harmonic distortions and spurs. A new ANN-based calibrator is designed to calibrate both single-channel nonlinearity and interchannel mismatches and significantly improve the performance of ADCs. Through signal-fitting-based training process and noise adding, the proposed mechanism and calibrator can calibrate the general nonlinearity and mismatches of ADCs, including but not limited to the typical nonideality that conventional calibration techniques commonly concern (such as interstage gain error, digital-to-analog converter (DAC) error, and timing mismatch). For verification, an on-chip ANN-based calibrator is implemented in a 12-bit 600-MS/s four-channel time-interleaved (TI) ADC prototype. The measurement results show that signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) are improved from 32.79 and 35.30 to 62.45 and 74.21 dB, respectively. Another off-chip ANN-based calibrator is applied to a commercial 12-bit 5.4-GS/s four-channel ADC, and the results show that the SNDR and SFDR are improved from 42.38 and 43.17 to 53.98 and 78.25 dB, respectively.

This paper presents a convolutional neural network (CNN) based error calibration scheme for pipelined ADC. The output of the pipelined ADC is taken as the input data of the network, and the network produces error compensation values. The network is applied in a 14-bit 1GSps pipelined ADC model with nonlinear errors including inter-stage gain error (IGE), DAC errors, thermal noise and sampling jitter for verification. The trained network scheme is verified with various types of signals including single-tone, dual-tone, amplitude modulation (AM) and frequency modulation (FM) signals. Simulation results show that, the SFDR and SNDR of the pipelined ADC are improved from 62.58dB and 58.82dB to 89.86dB and 66.66dB after calibration. Meanwhile, after calibration, the spurs of the dual-tone, AM and FM signals have been effectively suppressed.

This paper demonstrates a new neural-network-based calibration technique for inter-channel mismatches of time-interleaved ADCs. By providing with signal value and derivative value of each channel, the network could calibrate the gain mismatch, offset mismatch, and timing mismatch of TI-ADCs. By utilizing signal feature fitting, the ground truth for network training could be obtained without an accurate reference ADC nor a precise ADC error model. Simulation results show that the proposed calibration technique can increase the SFDR of a 14-bit 4Gsps TI-ADC from 32.77 dB to 91.71 dB for single-tone signals, and suppress the maximum spur from −48.51 dBFS to −101.23 dBFS for multi-tone signals. A hardware implementation resources estimation is also given in this paper.

This brief proposes a timing mismatch calibration for time-interleaved analog-to-digital converters (TI ADCs) with the novel parallel correlation derivative (PCD) technique and two-stage analog–digital hybrid compensation. The PCD technique could solve the frequency-relevant problem caused by low correlation derivative in the precise skew calculation. Besides, the compensation scheme with an analog coarse correction and then the all-digital fine correction is used to cover a larger normalized skew range and bandwidth with maintained calibration performance. Compared to previous works on timing mismatch calibration, this work has improved accuracy with a larger effective bandwidth and a larger skew calibration range. The technique is applied in a four-channel 14-bit 3 GS/s ADC model to verify its effectiveness. Simulation results show that it increases the SNDR and SFDR from 31.02 and 32.87 to 54.40 and 93.49 dB at${f}_{\text {in}}\,\,=\,\,0.99{f}_{s}$and maintains good performance in the first three Nyquist bands.

Power budget is an important power constraint provided to guarantee the thermal reliability of an integrated system. In this work, we present DBP, a distributed power budgeting method, for dark silicon many-core systems. In DBP, there are two new techniques proposed to bring accurate and optimized power budgets in a distributed way. First, a distributed active core locating technique is developed to find an active core distribution that leads to a high-power budget. Second, a distributed power budget computing technique is introduced which computes the power budget for each active core accurately. Experiments show DBP outperforms the state-of-the-art power budgeting methods’ thermal safe power (TSP) and greedy dynamic power (GDP) on many-core dark silicon systems by providing a high and accurate power budget with low overhead and good scalability.

This paper presents a bootstrapped switch with an accelerated gate-voltage rising speed and a reduced on- resistance for high-speed ADCs. Compared to the classic bootstrapped switch, this design accelerates the rising speed of gate voltage through four novel techniques. First, an extra NMOS transistor is added to pull up the gate voltage by injecting extra charges into the gate node. Second, the parasitic capacitance at the gate node is reduced by simplifying the circuit structure, leading to a faster speed. Third, transmission gates are used to reduce the two delays to one delay. Fourth, the voltage stored on the capacitor is increased to slightly larger than VDD, which leads to a faster gate-voltage rising speed as well as a larger value of gate voltage (about Vn+1.05 VDD). The larger gate voltage also helps reduce the on-resistance of the bootstrapped switch, which is helpful for the high-speed sampling of ADCs. In a 40 nm CMOS process, post-layout simulation results show that the rising speed of gate voltage is increased by 3.3 times compared to the classic thin-oxide bootstrapped switch circuit. And the on-resistance of the bootstrapped switch is reduced by 2.2 times compared to the classic structure, due to the larger gate voltage value.

A high-speed comparator constituted by a backgate-input latch and a pre-amplifier is proposed in this paper. Instead of using extra input transistors as in a classic StrongARM latch, the back-gate-input technique proposed in this paper obviates the need for extra input transistors in the latch stage, thus greatly reducing the parasitic capacitance and improving the comparator speed. Unlike the StrongARM latch where the amplification phase begins only after the CLK rises, the amplification phase in this paper begins before the CLK rises and replaces the reset phase, further improving the comparator speed. The pre-amplifier provides a gain of 22-dB, in order to suppress the input-referred noise and offset of the comparator. Designed in the same 22nm Silicon-on-Insulator (SOI) CMOS process for the proposed comparator and the conventional comparators, post-layout simulation results show that the performance in speed and input-referred noise are improved by 22% and 43%, respectively.

This brief presents a novel timing mismatch background calibration algorithm for time-interleaved (TI) analog-to-digital converters (ADCs). It can calibrate an arbitrary number of channels with an arbitrary input frequency. It also increases the calibration accuracy by applying the autocorrelation functions with an expanded interval. Besides, the proposed algorithm effectively prevents the small derivative values in the correlation difference from degrading the skew estimation accuracy. Compared to prior works on calibration, this work has at least five times better detection accuracy when the frequency of the input signal is close to the Nyquist frequency. This is without the need for calculating the high-order statistics. Finally, we simulate a four-channel 12-bit TI ADC with non-ideal effects added. Simulation results show that the proposed algorithm increases the signal to noise-plus-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) from 35.5 and 40.0 dB to 63.3 and 84.6 dB, respectively, when the input frequency is close to the Nyquist frequency.

This brief presents a three-stage comparator and its modified version to improve the speed and reduce the kickback noise. Compared to the traditional two-stage comparators, the three-stage comparator in this work has an extra amplification stage, which enlarges the voltage gain and increases the speed. Unlike the traditional two-stage structure that uses pMOS input pair in the regeneration stage, the three-stage comparator makes it possible to use nMOS input pairs in both the regeneration stage and the amplification stage, further increasing the speed. Furthermore, in the proposed modified version of three-stage comparator, a CMOS input pair is adopted at the amplification stage. This greatly reduces the kickback noise by canceling out the nMOS kickback through the pMOS kickback. It also adds an extra signal path in the regeneration stage, which helps increase the speed further. For easy comparison, both the conventional two-stage and the proposed three-stage comparators are implemented in the same 130-nm CMOS process. Measured results show that the modified version of three-stage comparator improves the speed by 32%, and decreases the kickback noise by ten times. This improvement is not at the cost of increased input referred offset or noise.

This paper proposes a low-power low-cost on-chip digital background calibration for a pipelined ADC. This new redundant-stage calibration algorithm reduces the effect of quantization noise and can be applied for multiple stages; hence, it improves the calibration accuracy and is easily implemented fully on-chip with low power and low hardware cost. We realize the proposed calibration technique in a prototype 12-bit 250-MS/s pipelined ADC fabricated in a 55-nm technology. The measured results show that the prototype ADC, with an active area of 1310 μm × 510 μm, achieves an signal-to-noise-and-distortion ratio of 66.7 dB [effective number of bits (ENOB) = 10.8 bit] and consumes a total power of 85 mW with a sampling rate of 250 MS/s after applying our digital calibration, where the on-chip digital calibration circuit consumes only 5 mW and an active area of 360 μm × 510 μm.

A novel voltage comparator, termed an edge-race comparator (ERC), is proposed in this article. It compares the differential input voltage by generating two propagating edges in two inverter loops and by measuring the distance between the two edges. The two edges race with each other and the winner is finally determined. The comparator is low power and low noise and does not require high-voltage headroom. It can automatically adjust its noise, power consumption, and delay according to the input voltage, thereby saving significant energy and time in coarse comparisons and reducing the noise in fine comparisons (noise averaging is performed over a longer time in fine comparisons). It is well suited for low-power, high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) (SAR ADCs). Compared to a recently published edge-pursuit comparator (EPC), the proposed structure achieves 3.39 times faster speed at 1-mV input by using a novel configuration of two inverter loops with a distance measurement circuit. The energy consumption per comparison is reduced by 2.73 times at 1-mV input owing to the shorter required comparison time. Designed in a standard 40-nm CMOS process, the measurement results from an ADC show that the comparator energy at the LSB is reduced by 7.5 times, and the ADC sampling rate is increased by 3.85 times.

This paper proposes a low-power low-cost on-chip digital background calibration for a pipelined ADC. This new redundant-stage calibration algorithm reduces the effect of quantization noise and can be applied for multiple stages; hence, it improves the calibration accuracy and is easily implemented fully on-chip with low power and low hardware cost. We realize the proposed calibration technique in a prototype 12-bit 250-MS/s pipelined ADC fabricated in a 55-nm technology. The measured results show that the prototype ADC, with an active area of 1310 gm × 510 gm, achieves an signal-to-noise-and-distortion ratio of 66.7 dB [effective number of bits (ENOB) = 10.8 bit] and consumes a total power of 85 mW with a sampling rate of 250 MS/s after applying our digital calibration, where the on-chip digital calibration circuit consumes only 5 mW and an active area of 360 gm × 510 gm.