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Loïc Thébault

dblp:145/3142 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 2018
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Parallel and multicore computing · 55% High-performance computing · 38% Processor architecture and microarchitecture · 7%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Parallel and multicore computing › parallel algorithms › parallel geometric algorithms
parallel mesh processing
0.212015
Scalable and efficient implementation of 3d unstructured meshes computation: a case study on matrix assembly · PPoPP 2015
Parallel and multicore computing
parallel programming models
0.212015
Scalable and efficient implementation of 3d unstructured meshes computation: a case study on matrix assembly · PPoPP 2015
High-performance computing
unstructured mesh computation
0.212015
Scalable and efficient implementation of 3d unstructured meshes computation: a case study on matrix assembly · PPoPP 2015
High-performance computing
domain decomposition
0.112015
Scalable and efficient implementation of 3d unstructured meshes computation: a case study on matrix assembly · PPoPP 2015
Parallel and multicore computing
load balancing
0.112015
Scalable and efficient implementation of 3d unstructured meshes computation: a case study on matrix assembly · PPoPP 2015
Processor architecture and microarchitecture
many-core architecture
0.112015
Scalable and efficient implementation of 3d unstructured meshes computation: a case study on matrix assembly · PPoPP 2015
High-performance computing › code optimization
vectorization
0.112015
Scalable and efficient implementation of 3d unstructured meshes computation: a case study on matrix assembly · PPoPP 2015

Methods — techniques the papers use, named apart from their topics

mesh coloring · 0.2domain decomposition · 0.2divide-and-conquer · 0.2
YearPublicationVenuePosition
2018 Asynchronous and multithreaded communications on irregular applications using vectorized divide and conquer approach
Loïc Thébault, Eric Petit 0002
J. Parallel Distributed Comput.1
2015 Scalable and efficient implementation of 3d unstructured meshes computation: a case study on matrix assembly
abstract
Exposing massive parallelism on 3D unstructured meshes computation with efficient load balancing and minimal synchronizations is challenging. Current approaches relying on domain decomposition and mesh coloring struggle to scale with the increasing number of cores per nodes, especially with new many-core processors. In this paper, we propose an hybrid approach using domain decomposition to exploit distributed memory parallelism, Divide-and-Conquer, D&C, to exploit shared memory parallelism and improve locality, and mesh coloring at core level to exploit vectors. It illustrates a new trade-off for many-cores between structuredness, memory locality, and vectorization. We evaluate our approach on the finite element matrix assembly of an industrial fluid dynamic code developed by Dassault Aviation. We compare our D&C approach to domain decomposition and to mesh coloring. D&C achieves a high parallel efficiency, a good data locality as well as an improved bandwidth usage. It competes on current nodes with the optimized pure MPI version with a minimum 10% speed-up. D&C shows an impressive 319x strong scaling on 512 cores (32 nodes) with only 2000 vertices per core. Finally, the Intel Xeon Phi version has a performance similar to 10 Intel E5-2665 Xeon Sandy Bridge cores and 95% parallel efficiency on the 60 physical cores. Running on 4 Xeon Phi (240 cores), D&C has 92% efficiency on the physical cores and performance similar to 33 Intel E5-2665 Xeon Sandy Bridge cores.
Loïc Thébault, Quang Dinh
PPoPP1