This brief implements a highly efficient fully differential transconductance amplifier, based on several input-to-output paths. Some traditional techniques, such as positive feedback, nonlinear tail current sources, and current mirror-based paths, are combined to increase the transconductance, thus leading to larger dc gain and higher gain bandwidth (GBW) product. Two flipped voltage-follower (FVF) cells are employed as variable current sources to provide class-AB operation and adaptive biasing of all other drivers. The proposed structure includes several input-to-output paths that play the role of dynamic current boosters during the slewing phase, thus improving the slew rate (SR) performance. The circuit was fabricated in a TSMC 0.18-$\mu \text{m}$CMOS process with a silicon area of$54.5\times 30.1\,\,\mu \text{m}$. Experimental results show a GBW of 173.3 MHz, a dc gain of 72.7 dB, and an SR of 139.4 V/$\mu \text{s}$for a capacitive load of$2\times5$pF. The proposed circuit consumes 619$\mu \text{W}$of power, under a supply voltage of 1.8 V.

This article presents the experimental results for a multiple-input operational transconductance amplifier (MI-OTA). To achieve extended linearity under 0.5-V low voltage supply, the circuit employs three linearization techniques: the bulk-driven (BD), the source degeneration, and the input voltage attenuation created by the MI metal-oxide-semiconductor transistor technique (MI-MOST). Although the linearization techniques result in reduced dc gain, the self-cascode transistors are used to boost the gain of the MI-OTA. Furthermore, the MI-MOST simplifies the internal structure of the OTA and may reduce the complexity of the applications. The MI-OTA operates in the subthreshold region and offers tunability by a bias current in the nanoampere range. The circuit is capable to work with 0.5-V supply voltage while consuming 24.77 nW. The circuit was fabricated using the 0.18-$\mu \text{m}$Taiwan Semiconductor Manufacturing Company (TSMC) CMOS technology and it occupies a 0.01153-mm2 silicon area. Intensive simulation and experimental results confirm the benefits and robustness of the design.

In this article, a new solution for an ultralow-voltage (ULV) ultralow-power (ULP) operational transconductance amplifier (OTA) is presented. Thanks to the combination of a low-voltage bulk-driven nontailed differential stage with the multipath Miller zero compensation technique, a simple class AB power-efficient ULV structure has been obtained, which can operate from supply voltages less than the threshold voltages of the employed MOS transistors, while offering rail-to-rail input common-mode range at the same time. The proposed OTA was fabricated using the 180-nm CMOS process from Taiwan Semiconductor Manufacturing Company (TSMC) and can operate from VDD ranging from 0.3 to 0.5 V. The 0.3-V version dissipates only 12.6 nW of power while showing a 64.7-dB voltage gain at 1-Hz, 2.96-kHz gain-bandwidth product, and a 4.15-V/ms average slew-rate at 30-pF load capacitance. The measured results agree well with simulations.

A new solution for an ultralow-voltage bulkdriven (BD) asynchronous delta-sigma modulator is described in this paper. While implemented in a standard 0.18-μm CMOS process from the Taiwan Semiconductor Manufacturing Company and supplied with VDD = 0.3 V, the circuit offers a 53.3-dB signal-to-noise and distortion ratio, which corresponds to 8.56-bit resolution. In addition, the total power consumption is 37 nW, the signal bandwidth is 62 Hz, and the resulting power efficiency is 0.79 pJ/conversion. The above-mentioned features have been achieved employing a highly linear transconductor and a hysteretic comparator based on nontailed BD differential pair.