The design of level shifters for high-voltage and high-speed applications must achieve low propagation delays while maintaining high immunity to power supply slew rates. A novel floating voltage level shifter with rapid operation, high power supply slew tolerance, and almost zero static power consumption is introduced. The conversion principle of the circuit is comprehensively analyzed. Additionally, a series of innovative optimization techniques are implemented to enhance switching speed and power supply slew tolerance, eliminate the asymmetry of rise and fall delays, and reduce power consumption and silicon area. The level shifter is designed using 0.18μm BCD technology, and post-layout simulations are performed by extracting parasitic parameters. The simulation results indicate that, at a level-shifting voltage of 45V, the proposed level-shifter achieves a propagation delay of 0.76ns, 300 V/ns ofdVSSH/dtslew rate immunity, and a single transition energy of 31.2pJ, with near-symmetrical rise and fall propagation delays.

Hybrid DC circuit breakers (HDCCBs) are among the most promising solutions for DC breaking. HDCCBs based on forced commutation have the shortcomings of conduction loss or high cost, which hinders their large-scale application. HDCCBs based on natural commutation, despite their lower cost and smaller volume, are limited by the arc voltage. Therefore, this paper proposes a type of multibreak mechanical switch applicable for medium-voltage natural commutation HDCCBs. Possessing the advantages of compact size and high arc voltage, the switch consists of a four-break gas chamber and a vacuum chamber, the former of which realizes the series connection of multiple arcs through a bridge contact structure. The vacuum chamber is used to bear the turn-off overvoltage. Combined with high-speed observation methods, the mechanical characteristics and arc characteristics of the multibreak mechanical switch are analyzed, and the influence mechanism of different factors on the arc characteristics of the four-break chamber is revealed. On this basis, a principle prototype of the 15 kV medium-voltage natural commutation HDCCB was developed, and breaking tests were carried out. The breaking current can reach 15 kA, and the breaking time is less than 3 ms.

This paper develops a novel graph convolutional network (GCN) framework for fault location in power distribution networks. The proposed approach integrates multiple measurements at different buses while taking system topology into account. The effectiveness of the GCN model is corroborated by the IEEE 123 bus benchmark system. Simulation results show that the GCN model significantly outperforms other widely-used machine learning schemes with very high fault location accuracy. In addition, the proposed approach is robust to measurement noise and data loss errors. Data visualization results of two competing neural networks are presented to explore the mechanism of GCNs superior performance. A data augmentation procedure is proposed to increase the robustness of the model under various levels of noise and data loss errors. Further experiments show that the model can adapt to topology changes of distribution networks and perform well with a limited number of measured buses.

DC fault protection is one of the biggest challenge to multi-terminal direct current (MTDC) systems, because DC current has no natural zero crossing point. To overcome this problem, hybrid DC circuit breaker (DCCB), which serves as a promising solution to the isolation of DC faults, has been developed. However, hybrid DCCB contains a huge number of power semiconductors, which is costly and inefficient especially in MTDC. This paper proposed a novel hybrid DCCB for nodes in MTDC system. By optimizing the topology and corresponding control strategy of traditional hybrid DCCB, the requirement of power semiconductors is reduced without degrading the performance. The novel hybrid DCCB is verified by simulations of a four-terminal radial DC grid with MATLAB/Simulink.