Computing modules in typical data center nodes or server racks consist of several multicore chips either on a board or in a System-in-Package (SiP) environment. State-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the destination chip over a wireline interconnect fabric. This multihop communication increases energy consumption while decreasing data bandwidth in a multichip system. Also, traditional I/O does not scale well with technology generations due to limitations of pitch. Moreover, intra-chip and inter-chip communication protocol within such a multichip system is often decoupled to facilitate design flexibility. However, a seamless interconnection between on-chip and off-chip data transfer can improve the communication efficiency significantly. Here, we propose the design of a seamless hybrid wired and wireless interconnection network for multichip systems with dimensions spanning up to tens of centimeters with on-chip wireless transceivers. We demonstrate with cycle accurate simulations that such a design increases the bandwidth and reduces the energy consumption in comparison to state-of-the-art wireline I/O based multichip communication.

With increase in complexity of multicore chips, efficiency of data transfer between cores of a chip is becoming increasingly challenging. Several novel on-chip network architectures are proposed to improve the design flexibility and communication efficiency in multicore chips. On the other hand, computing modules in typical data center nodes or server racks consist of several multicore chips on either a board or in a System-in-Package (SiP) environment. State-of-the-art interchip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the interchip channels to the destination chip. After reaching the destination chip they will be finally routed from the I/O to the internal nets there. This multihop communication increases latency and energy consumption while decreasing data bandwidth in a multichip system. Moreover, intrachip and interchip communication within such a multichip system is often decoupled to facilitate design flexibility. However, a seamless interconnection between on-chip and off-chip data transfer can improve the communication efficiency significantly. In this work we propose the design of a seamless hybrid wired and wireless interconnection network for multichip systems in a package with dimensions spanning up to tens of centimeters with on-chip wireless transceivers. This enables direct chip-to-chip communication between internal cores. We demonstrate with cycle accurate simulations that such a design increases the bandwidth and reduces the energy consumption in comparison to state-of-the-art wireline I/O based multichip communication.

On-chip wireless interconnects have emerged as a promising alternative to conventional wireline interconnects in Network-on-Chip (NoC) fabrics for multicore systems. However, it is not practical in the immediate future to arbitrarily scale up the number of wireless links without innovations in the physical layer. Here, we explore the design of a directional on-chip antenna based on a log-periodic structure. In this paper we propose the design of a wireless NoC (WiNoC) architecture with concurrent wireless links using these directional on-chip antennas. Through cycle accurate simulations we demonstrate that this novel WiNoC architecture attains better performance and energy efficiency compared to the state-of-the-art token based WiNoC of similar topology.