Demo Data from EDBT 2026 / reviewers in the wild / expert
Ulrike Schorr
dblp:145/9304
· DBLP profile ↗
5ranked-venue papers
0as first author
2since 2021 · last 2023
0000-0002-0796-1969ORCID · corroborated
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 5 · 2 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 100% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.4 | 2 | 2015 | Local search algorithms for timing-driven placement under arbitrary delay models · DAC 2015 Post-Routing Latch Optimization for Timing Closure · DAC 2014 |
Electronic design automation › logic synthesis › technology mapping
cell selection |
0.3 | 1 | 2018 | Provably Fast and Near-Optimum Gate Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Electronic design automation › physical design
gate sizing |
0.3 | 1 | 2018 | Provably Fast and Near-Optimum Gate Sizing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2018 |
Electronic design automation › physical design
placement |
0.2 | 1 | 2015 | Local search algorithms for timing-driven placement under arbitrary delay models · DAC 2015 |
Electronic design automation › physical design › placement
timing-driven placement |
0.2 | 1 | 2015 | Local search algorithms for timing-driven placement under arbitrary delay models · DAC 2015 |
Electronic design automation › physical design
timing optimization |
0.1 | 1 | 2014 | Post-Routing Latch Optimization for Timing Closure · DAC 2014 |
Methods — techniques the papers use, named apart from their topics
parallelization · 0.3multiplicative weight update · 0.3lagrangian relaxation · 0.3slack optimization · 0.2local search · 0.2
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2023 | A Fast Optimal Double-row Legalization AlgorithmabstractIn Placement Legalization, it is often assumed that (almost) all standard cells possess the same height and can therefore be aligned in cell rows , which can then be treated independently. However, this is no longer true for recent technologies, where a substantial number of cells of double- or even arbitrary multiple-row height is to be expected. Due to interdependencies between the cell placements within several rows, the legalization task becomes considerably harder. In this article, we show how to optimize squared cell movement for pairs of adjacent rows comprising cells of single- as well as double-row height with a fixed left-to-right ordering in time 𝒪( n · log ( n )), where n denotes the number of cells involved. Opposed to prior works, we do not artificially bound the maximum cell movement and can guarantee to find an optimum solution. Our approach also allows us to include gridding and movebound constraints for the cells. Experimental results show an average percental decrease of over 26% in the total squared movement when compared to a legalization approach that fixes cells of more than single-row height after Global Placement. Stefan Hougardy, Meike Neuwohner, Ulrike Schorr |
ACM Trans. Design Autom. Electr. Syst. | 3 |
| 2021 | A Fast Optimal Double Row Legalization AlgorithmabstractIn Placement Legalization, it is often assumed that (almost) all standard cells possess the same height and can therefore be aligned in cell rows, which can then be treated independently. However, this is no longer true for recent technologies, where a substantial number of cells of double- or even arbitrary multiple-row height is to be expected. Due to interdependencies between the cell placements within several rows, the legalization task becomes considerably harder. In this paper, we show how to optimize quadratic cell movement for pairs of adjacent rows comprising cells of single- as well as double-row height with a fixed left-to-right ordering in time $\mathcalO (n\cdotłog(n))$, whereby n denotes the number of cells involved. Opposed to prior works, we thereby do not artificially bound the maximum cell movement and can guarantee to find an optimum solution. Experimental results show an average percental decrease of over $26%$ in the total quadratic movement when compared to a legalization approach that fixes cells of more than single-row height after Global Placement. Stefan Hougardy, Meike Neuwohner, Ulrike Schorr |
ISPD | 3 |
| 2018 | Provably Fast and Near-Optimum Gate SizingabstractWe present a new approach for the cell selection problem based on a resource sharing formulation, which is a specialization of Lagrangian relaxation with multiplicative weight updates. For the convex continuous gate sizing problem, we can prove fast polynomial running times. This theoretical result also gives some justification to previous heuristic multiplicative weight update methods. For the discrete cell selection problem, where voltage thresholds can also be chosen, we employ the new algorithm heuristically and achieve superior results on industrial benchmarks compared with one of the previously best known algorithms, and competitive results on the ISPD 2013 benchmarks. Finally, we demonstrate how the approach can be parallelized effectively achieving speed-ups of up to 16. Siad Daboul, Nicolai Hähnle, Stephan Held, Ulrike Schorr |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 4 |
| 2015 | Local search algorithms for timing-driven placement under arbitrary delay modelsabstractWe present local search algorithms for timing-driven placement optimization. They find local slack optima for cells under arbitrary delay models and can be applied late in the design flow. Adrian Bock, Stephan Held, Nicolas Kämmerling, Ulrike Schorr |
DAC | 4 |
| 2014 | Post-Routing Latch Optimization for Timing ClosureabstractWe present an algorithm which permutes latch positions and sizes within a clock cluster to maximize the worst slack. It preserves the clock footprint and routing, and can therefore be applied late in the design flow after clock network design. Stephan Held, Ulrike Schorr |
DAC | 2 |