Physically unclonable function (PUF) is one of the critical security primitives for key generation and storage. The key challenge in building a PUF is to achieve high robustness against noise, temperature/supply voltage (VDD) variations and device aging with low cost. This paper presents a technique to transform a pre-existing SRAM array into an analog PUF by configuring the access transistors in a 6T-SRAM bitcell into a pair of threshold voltage (Vth) sensors and comparing their outputs. The proposed analog PUF circuit achieves significantly better robustness than conventional SRAM-based PUFs using reset states while maintaining the benefit of hardware reuse: low area overhead. Test chips are prototyped in a 65nm CMOS to verify the randomness, uniqueness, and robustness of the proposed design.

This paper explores the models of the energy-optimal voltage (VOPT) of near/sub-threshold digital VLSI circuits with a focus on the support for a wide range of nodal switching rates. The previous models can estimate the VOPTof the circuits having relatively high nodal switching rates (VOPT, H), but can become inaccurate in finding the VOPT of the circuits having low nodal switching rate. In this work, therefore, we develop the models for finding (i) the VOPTof the circuits having low nodal switching rates (VOPT, L) and (ii) the critical nodal switching rate point (αcrit) below which the VOPT, Lshould be used. The models are verified with inverter chains and sub-threshold 10-transistor SRAM arrays in SPICE-level simulation. The model takes only process technology parameters to estimate VOPTs, and can be suitable for early-stage design-space exploration.

Runtime monitoring of aging effects in pipeline circuits is the key to dynamic reliability management techniques which can maximize the performance and energy-efficiency under a reliability envelope without imposing worst-case margin. The existing monitoring techniques are, however, severely limited: for sensor-based techniques, monitoring accuracy is significantly compromised due to the mismatches in aging conditions between sensors and the target circuits, as well as random variation of aging effects; for in-situ techniques, measurement results are sensitive to environmental variations during test phases, also severely reducing monitoring accuracy. We propose a new technique that enables accurate in-situ aging monitoring even under large environmental variations by (i) scaling the supply voltage for temperature-insensitive delay and (ii) reconfiguring target paths into ring oscillators, whose oscillation periods are measured and compared to pre-aging measurement to estimate aging-induced delay degradations. With additional accuracy-improving strategies, the technique achieves highly-accurate monitoring with an error of 15.5% across the temperature variations in self-test phases from 0°C to 80°C, exhibiting >30× improvement in accuracy as compared to the conventional technique operating at nominal supply voltage.