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Meng-Yen Chuang

dblp:145/9370 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 2016
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Storage systems · 69% Hardware reliability and fault tolerance · 31%
Theoretical computer science
1 paper
Coding theory · 100%

Topics — the 9 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware reliability and fault tolerance › error correction
cache error correction
0.422016
Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality · IEEE Trans. Computers 2016
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs · DAC 2014
Storage systems
flash and SSD
0.422016
Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality · IEEE Trans. Computers 2016
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs · DAC 2014
Storage systems › flash and SSD › solid-state drive
flash-based SSD
0.212016
Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality · IEEE Trans. Computers 2016
Storage systems › flash and SSD › flash memory
LDPC decoding
0.212014
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs · DAC 2014
Storage systems › flash and SSD › flash memory reliability
NAND flash error correction
0.212014
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs · DAC 2014
Coding theory
error-correcting codes
0.112016
Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality · IEEE Trans. Computers 2016
Coding theory › error-correcting codes › LDPC codes
LDPC decoding
0.112016
Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality · IEEE Trans. Computers 2016
Hardware reliability and fault tolerance › error correction
error-correcting codes
0.112014
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs · DAC 2014
Storage systems
storage reliability
0.112014
EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs · DAC 2014

Methods — techniques the papers use, named apart from their topics

error locality exploitation · 0.7SSD simulation · 0.5LDPC simulation · 0.5low-density parity-check code · 0.2
YearPublicationVenuePosition
2016 Improving Read Performance of NAND Flash SSDs by Exploiting Error Locality
abstract
NAND flash-based solid-state drives (SSDs), which can serve as the caches of hard disk drives, have gained popularity in large-scale, high-performance storage. A type of advanced error correction code for SSDs, low-density parity-check (LDPC), is required to mitigate a considerable number of errors in the raw data of NAND flash. However, LDPC imposes read performanceoverhead due to the complex decoding procedure of LDPC. In this paper, we propose an error-correcting cache (EC-Cache) that exploits “error locality”, a characteristic of NAND flash memory, to improve the read performance of SSDs. We use the term “error locality” to refer to the property that the majority of errors in reads to the same flash page appear at the same positions until thepage is erased. By caching detected errors, we can correct a significant portion of errors in the requested flash page prior to the LDPC decoding process. This design significantly reduces LDPC decoding overhead because the latency of LDPC is correlated with thenumber of errors in the input data. We conduct experiments, including flash characterization, LDPC simulation, and SSD simulation,to evaluate EC-Cache. The experimental results demonstrate that EC-Cache can improve the read performance of LDPC-based SSDs by up to$2.6\times$.
Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li
IEEE Trans. Computers2
2014 EC-Cache: Exploiting Error Locality to Optimize LDPC in NAND Flash-Based SSDs
abstract
Low-density parity-check (LDPC) is widely accepted as the baseline error-correction codes offering strong error-correcting capability for future NAND flash-based SSDs. However, LDPC incurs read performance overhead because of its complex decoding procedure. To mitigate such overhead, we propose the error-correcting cache (EC-Cache) that exploits the "error locality" of NAND flash. Error locality means that the majority of errors in reads to the same NAND flash page appear in the same positions until the page is erased. By caching detected errors, EC-Cache can correct a significant portion of errors present in a requested flash page before the associated LDPC decoding process begins. EC-Cache can greatly speed up LDPC decoding because LDPC's latency is directly correlated to the number of errors present in the input data. Experimental results show that EC-Cache achieves up to 2.6× SSD read performance gain.
Ren-Shuo Liu, Meng-Yen Chuang, Chia-Lin Yang, Cheng-Hsuan Li, Kin-Chu Ho, Hsiang-Pang Li
DAC2