The Computing-In-Memory (CIM) paradigm offers a promising solution to the memory-wall bottleneck that limits conventional Von Neumann architectures. By performing data processing at the same physical location where the data are stored, CIM-based architectures minimize costly data movement and drastically improve energy efficiency. When implemented with Ferroelectric Field Effect Transistors (FeFETs), additional advantages from the non-volatility, fast switching, and low operating voltage of FeFETs are added. However, the widespread adoption of FeFETs is limited by their poor endurance, which is overcome by a Back End of the Line (BEoL) integration of FeFET-2, where a ferroelectric capacitor (FeCAP) is wired to the gate of a CMOS transistor providing high endurance compatible with low-power edge applications. These properties enable dense, low-power, and high-speed matrix operations essential for AI workloads. As a result, FeFET-2-based CIM accelerators offer a promising solution for energy-efficient, high-performance AI at the edge. The Ferro4EdgeAI project aims to develop an ultra low-power, scalable edge accelerator for AI, targeting a significant gain in energy efficiency with respect to state-of-the-art AI hardware accelerators. To attain this, our project focuses on innovation all along the value chain from materials, physic concepts, device architecture, integration technologies, and accelerators in a holistic design space exploration approach.

The electrical engineering community, interested to develop bio-inspired circuits, approaching the efficiency of the neural networks, is searching passionately for accurate yet simple electronic neurons, or neuristors for short. In recent years, the advent of volatile memristor devices, typically referred to as threshold switches, which admit a negative differential resistance under suitable polarization, similarly as the sodium and potassium ion channels across neuronal axon membranes, has opened up new exciting opportunities in neuromorphic circuit design, enabling innovative analogue electronic cells, capable to reproduce closely the intricate dynamical behaviors of biological neurons without requiring a disproportionate use of resources. The study, presented in this manuscript, achieves an important milestone in this area of research, demonstrating, through a circuit design approach based upon concepts and techniques from Dynamical System Theory, how to leverage the rich dynamics of a threshold switch, capable to boost a periodic sine-wave current signal of infinitesimal amplitude, while acting as a source of local energy, when poised on a suitable bias point, lying along the negative differential resistance branch of the respective S-shaped DC current-voltage characteristic, to induce, one after the other, the three fundamental bifurcations, governing the evolution of an electrical voltage spike from birth to extinction via the All-to-None effect across a biological axon membrane under a reverse sweep in the net synaptic current, according to the fourth-order Hodgkin-Huxley neuron model, in a second-order three-element circuit of unprecedented simplicity, as the current, generated by a DC source, appearing in parallel to a linear capacitor as well as to the volatile locally-active memristor, is subject to a monotonic increase.

This manuscript sheds light into the fundamental importance of the Principles of Local Activity and Edge of Chaos for the future design of innovative circuits, which, employing biomimetic memristive devices, are ideally suited for the development of energy-efficient artificially-intelligent technical systems. The focus of the work is the design of a Second-Order Reactance-Less Oscillator, across which oscillations may develop if and only if at least one of its two different volatile thermally-activated memristor physical realizations is biased along a negative differential resistance branch of the respective DC locus, which turns it into a source of local energy. Very importantly, the proposed cell is first found to lock in the oscillatory mode out of a local Hopf Supercritical Bifurcation when its design parameters are chosen from the Edge of Chaos region, providing clear evidence for the high degree of excitability it acquires as a result.

Novel non-volatile memory devices based on ferroelectric thin films represent a promising emerging technology that is ideally suited for neuromorphic applications. The physical switching mechanism in such films is the nucleation and growth of ferroelectric domains. Since this has a strong dependence on both pulse width and voltage amplitude, it is important to use precise pulsing schemes for a thorough characterization of their behavior. In this work, we present an on-chip 120 dB programmable range pulse generator, that can generate pulse widths ranging from 10 ns to 10 ms ± 2.5% which eliminates the RLC bottleneck in the device characterisation setup. We describe the pulse generator design and show how the pulse width can be tuned with high accuracy, using Digital to Analog converters. Finally, we present experimental results measured from the circuit, fabricated using a standard 180 nm CMOS technology.

This paper proposes the derivation of a physics-based model of an analog memristive device realized as a bi-layer Al2O3/NB2O5stack. Memristive crossbar arrays implementing matrix-vector multiplications are a central building block of novel computing-in-memory architectures for artificial neural network and neuromorphic computing applications. The presented memristor shows analog, multi-level switching at high resistances without electroforming and is suitable for crossbar operations with low energy consumption. By including a graphical analysis method of the I-V curves obtained in a quasi-static approach, the dynamic behavior is analyzed with regard to ohmic and Poole-Frenkel behavior. Finally, a compact model, represented by an algebraic differential equation, is proposed and verified by fitting calculated solutions to experimental data.

Ferroelectric field effect transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low-power, and non-volatile memories. In this paper, we propose a memory architecture named crossed-AND (C-AND), in which each storage cell consists of a single ferroelectric transistor. The write operation is performed using different write schemes and different absolute voltages, to account for the asymmetric switching voltages of the FeFET. It enables writing an entire wordline in two consecutive cycles and prevents current and power through the channel of the transistor. During the read operation, the current and power are mostly sensed at a single selected device in each column. The read scheme additionally enables reading an entire word without read errors, even along long bitlines. Our Simulations demonstrate that, in comparison to the previously proposed AND architecture, the C-AND architecture diminishes read errors, reduces write disturbs, enables the usage of longer bitlines, and saves up to 2.92X in memory cell area.

Ferroelectric tunneling junctions (FTJ) are considered to be the intrinsically most energy efficient memristors. In this work, specific electrical features of ferroelectric hafnium-zirconium oxide based FTJ devices are investigated. Moreover, the impact on the design of FTJ-based circuits for edge computing applications is discussed by means of two example circuits.

The main focus of this paper is the presentation of reliable methods for the determination of the optimum coloring of a graph, commonly known in the literature as vertex coloring problem. It has been shown that networks of capacitively coupled oscillators can be used to solve vertex coloring problems. In this paper we address the negative impact of an unbalanced number of couplings for the oscillators on the performance of the network and compensate for this non-uniform coupling structure by an adjustment in the network itself. The negative effect of the memristor device-to-device variability of the NbOxmemristor on the array functionality will be investigated and reduced via an adaptation of the memristor operating point. The main improvement in network performance is achieved by setting up a control procedure allowing the network to bypass the local solutions and converge to the global one. Two strategies inspired by global optimization algorithms will be proposed to allow the network to overcome sub-optimal solutions, and find the solution corresponding to the absolute minimum of a performance measure function of the vertex coloring problem.

Recently, memory and logic were brought into closer vicinity by introducing Logic-in-Memory circuits based on ferroelectric FETs (FeFET), where the FeFET not only stores logic values in its ferroelectric layer, but also performs logic operations of externally applied inputs with these internally stored values. As one reason for using these structures is to overcome the von-Neumann bottleneck, their logic readout gained a lot of attention, while the storage of the calculated outputs was neglected. In this paper, we propose to utilize two intercoupled memory arrays for this purpose. Between these, three operation modes are possible: pure memory operation, a passing of bits through the structure (logic mode), and conducting a logic operation in cells of the first memory array, whose result is stored in the cells of the second memory array, directly combining the logic and memory capability of these structures. For the latter, we suggest a suitable operation scheme. Electrical measurements of 28nm HKMG FeFET test structures based on hafnium oxide (HfO2) confirm the feasibility of the proposed logic/memory mixed mode.

In this paper, we consider devices, circuits, and systems comprised of transistors with integrated ferroelectrics. Said structures are actively being considered by various semiconductor manufacturers as they can address a large and unique design space. Transistors with integrated ferroelectrics could (i) enable a better switch (i.e., offer steeper subthreshold swings), (ii) are CMOS compatible, (iii) have multiple operating modes (i.e., I-V characteristics can also enable compact, 1-transistor, non-volatile storage elements, as well as analog synaptic behavior), and (iv) have been experimentally demonstrated (i.e., with respect to all of the aforementioned operating modes). These device-level characteristics offer unique opportunities at the circuit, architectural, and system-level, and are considered here from device, circuit/architecture, and foundry-level perspectives.

Logic-in-memory circuits promise to overcome the von-Neumann bottleneck, which constitutes one of the limiting factors to data throughput and power consumption of electronic devices. In the following we present four-input logic gates based on only two ferroelectric FETs (FeFETs) with hafnium oxide as the ferroelectric material. By utilizing two complementary inputs, a XOR and a XNOR gate are created. The use of only two FeFETs results in a compact and nonvolatile design. This realization, moreover, directly couples the memory and logic function of the FeFET. The feasibility of the proposed structures is revealed by electrical measurements of HKMG FeFET memory arrays manufactured in 28nm technology.

Edge computing requires highly energy efficient microprocessor units with embedded non-volatile memories to process data at IoT sensor nodes. Ferroelectric non-volatile memory devices are fast, low power and high endurance, and could greatly enhance energy-efficiency and allow flexibility for finer grain logic and memory. This paper will describe the basics of ferroelectric devices for both hysteretic (non-volatile memory) and negative capacitance (steep slope switch) devices, and then project how these can be used in low-power logic cell architectures and fine-grain logic-in-memory (LiM) circuits.

Resistive switching devices have a high potential for nonvolatile memories and circuit applications. This paper gives a review of the different switching modes in niobium oxide. Abrupt memory switching, threshold switching with or without memory switching and analog switching can be obtained by controlling the stoichiometry of the layer stack either with the use of reactive electrodes, by reactive sputtering with different argon to oxygen ratios or by ion implantation.

In this paper1a stability analysis sheds light into aspects of memristor circuit design, revealing a circuit theoretic technique for the stabilization of the NDR portion of the device DC characteristic. This type of studies supports the work of designers exploring memristor potential in electronics. Concepts from nonlinear dynamics theory allow us to gain a deep understanding of the dynamics of our locally-active memristor. The analysis provides hints on how to design an oscillator where limit-cycle behavior emerges from the locally-active threshold switching of the memristor, as theoretically proved here.