Abstract Existing iterative compilation and machine learning-based optimization techniques have been proven very successful in achieving better optimizations than the standard optimization levels of a compiler. However, they were not engineered to support the tuning of a compiler’s optimizer as part of the compiler’s daily development cycle. In this paper, we first establish the required properties that a technique must exhibit to enable such tuning. We then introduce an enhancement to the classic nightly routine testing of compilers, which exhibits all the required properties and thus is capable of driving the improvement and tuning of the compiler’s common optimizer. This is achieved by leveraging resource usage and compilation information collected while systematically exploiting prefixes of the transformations applied at standard optimization levels. Experimental evaluation using the LLVM v6.0.1 compiler demonstrated that the new approach was able to reveal hidden cross-architecture and architecture-dependent potential optimizations on two popular processors: the Intel i5-6300U and the Arm Cortex-A53-based Broadcom BCM2837 used in the Raspberry Pi 3B+. As a case study, we demonstrate how the insights from our approach enabled us to identify and remove a significant shortcoming of the CFG simplification pass of the LLVM v6.0.1 compiler.

This work proposes a novel methodology to predict the optimal performance and energy efficiency trade-off configurations of parallel applications running on a two-cluster Heterogeneous Multi-Processing (HMP) system. we propose an analytic performance and power model that are generated offline using data measurements. These models are then used to estimate the whole configuration space to predict the application's performance and energy consumption. Then, we use these off-line predictions to choose Pareto-optimal configurations, which is the most efficient among all configurations for the given architecture and multi-threaded application. We validated our methodology on an ODROID XU3 board on several PARSEC and Phoronix Test Suite applications.

The critical path delay and, as a consequence, the maximum operating frequency of a digital system are dependent on the supply voltage, so is its power consumption. Typically, voltage guard bands are added in order to improve reliability, at the expense of power efficiency. It has been shown that error detection and correction (EDAC) techniques can be used to mitigate the effects of the reduced safety margins. This Ph.D. project aims to develop a MPSoC capable of self regulate its operating voltage by monitoring the error rate reported by a EDAC system, virtually eliminating voltage safety margins. Literature review and preliminary experiments supports the viability of this approach, motivating further investigation.

This paper presents the interesting observation that by performing fewer of the optimizations available in a standard compiler optimization level such as -02, while preserving their original ordering, significant savings can be achieved in both execution time and energy consumption. This observation has been validated on two embedded processors, namely the ARM Cortex-M0 and the ARM Cortex-M3, using two different versions of the LLVM compilation framework; v3.8 and v5.0. Experimental evaluation with 71 embedded benchmarks demonstrated performance gains for at least half of the benchmarks for both processors. An average execution time reduction of 2.4% and 5.3% was achieved across all the benchmarks for the Cortex-M0 and Cortex-M3 processors, respectively, with execution time improvements ranging from 1% up to 90% over the -02. The savings that can be achieved are in the same range as what can be achieved by the state-of-the-art compilation approaches that use iterative compilation or machine learning to select flags or to determine phase orderings that result in more efficient code. In contrast to these time consuming and expensive to apply techniques, our approach only needs to test a limited number of optimization configurations, less than 64, to obtain similar or even better savings. Furthermore, our approach can support multi-criteria optimization as it targets execution time, energy consumption and code size at the same time.

Energy transparency is a concept that makes a program’s energy consumption visible, from hardware up to software, through the different system layers. Such transparency can enable energy optimizations at each layer and between layers, as well as help both programmers and operating systems make energy-aware decisions. In this article, we focus on deeply embedded devices, typically used for Internet of Things (IoT) applications, and demonstrate how to enable energy transparency through existing static resource analysis (SRA) techniques and a new target-agnostic profiling technique, without hardware energy measurements. Our novel mapping technique enables software energy consumption estimations at a higher level than the Instruction Set Architecture (ISA), namely the LLVM intermediate representation (IR) level, and therefore introduces energy transparency directly to the LLVM optimizer. We apply our energy estimation techniques to a comprehensive set of benchmarks, including single- and multithreaded embedded programs from two commonly used concurrency patterns: task farms and pipelines. Using SRA, our LLVM IR results demonstrate a high accuracy with a deviation in the range of 1% from the ISA SRA. Our profiling technique captures the actual energy consumption at the LLVM IR level with an average error of 3%.

People do most of their activities, business, commerce, entertainment and socializing indoors. As all of these are increasingly aided by online services and indoor spaces are becoming bigger and more complex, there is a growing need for cost-effective indoor localization, mapping, navigation and information services. In this paper, we present a complete Indoor Information Service, coined Anyplace, which has an open, modular, extensible and scalable architecture, making it ideal for a wide range of applications. Our service features three highly desirable properties, namely crowd sourcing, scalability and accuracy. Anyplace implements a set of crowd sourcing-supportive mechanisms to handle the enormous amount of crowd-sensed data, filter incorrect user contributions and exploit Wi-Fi data from heterogeneous mobile devices. Moreover, it uses a big-data architecture for efficient storage and retrieval of localization and mapping data. Finally, our service relies on the abundance of sensory data on smartphones (e.g., Wi-Fi signal strength and inertial measurements) to deliver reliable indoor geolocation information that received several international awards.

Energy models can be constructed by characterizing the energy consumed when executing each instruction in a processor's instruction set. This can be used to determine how much energy is required to execute a sequence of assembly instructions, without the need to instrument or measure hardware.