Abdalhossein Rezai

dblp:146/0978 · DBLP profile ↗
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6ranked-venue papers
2as first author
3since 2021 · last 2026
0000-0001-8529-499XORCID · corroborated

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 1 first-author · 3 since 2021Security and privacy · 1 · 1 first-author
YearPublicationVenuePosition
2026 A new circuit design for serial input-serial output shift registers with two controllable inverting outputs in QCA technology
Mojtaba Niknezhad Divshali, Abdalhossein Rezai
Integr.2
2025 Design of new single-bit multilayer ALU in QCA technology
Reza Faraji, Abdalhossein Rezai
Integr.2
2024 Design of a multilayer reversible ALU in QCA technology
Reza Faraji, Abdalhossein Rezai
J. Supercomput.2
2018 A novel design for ultra-low power pulse-triggered D-Flip-Flop with optimized leakage power
Ahmad Karimi, Abdalhossein Rezai, Mohammad Mahdi Hajhashemkhani
Integr.2
2016 Advance hybrid key management architecture for SCADA network security
abstract
Abstract This paper presents and evaluates an advance hybrid key management architecture for supervisory control and data acquisition (SCADA) networks (HSKMA), which supports all three types of communications: unicast, multicast, and broadcast. The HSKMA is based on the elliptic curve cryptography and symmetric cryptography. While the elliptic curve cryptography is used for communication between master station unit (MSU) and sub‐MSUs, the symmetric cryptographic algorithm is used for communication between sub‐MSUs and slave stations that have limited computational resources. Our analysis shows that the HSKMA has the following distinctive advantages: 1) it supports the security requirement such as availability, forward security, and backward security, 2) it supports the required speed in the MODBUS implementation, and 3) it is suitable for the environments that have limited computational resources. Copyright © 2016 John Wiley & Sons, Ltd.
Abdalhossein Rezai, Parviz Keshavarzi, Zahra Moravej
Secur. Commun. Networks1
2015 High-Throughput Modular Multiplication and Exponentiation Algorithms Using Multibit-Scan-Multibit-Shift Technique
abstract
Modular exponentiation with a large modulus and exponent is a fundamental operation in many public-key cryptosystems. This operation is usually accomplished by repeating modular multiplications. Montgomery modular multiplication has been widely used to relax the quotient determination. The carry-save adder has been employed to reduce the critical path. This paper presents and evaluates a new and efficient Montgomery modular multiplication architecture based on a new digit serial computation. The proposed architecture relaxes the high-radix partial multiplication to a binary multiplication. It also performs several multiplications of consecutive zero bits in one clock cycle instead of several clock cycles. Moreover, the right-to-left and left-to-right modular exponentiation architectures have been modified to use the proposed modular multiplication architecture as its structural unit. We provide the implementation results on a Xilinx Virtex 5 FPGA demonstrating that the total computation time and throughput rate of the proposed architectures outperform most results so far in the literatures.
Abdalhossein Rezai, Parviz Keshavarzi
IEEE Trans. Very Large Scale Integr. Syst.1