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Yaohung M. Tsai

dblp:146/1330 · DBLP profile ↗
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3ranked-venue papers
0as first author
0since 2021 · last 2019
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2Applied, interdisciplinary, general and emerging computing · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
High-performance computing · 90% GPUs and heterogeneous computing · 10%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing › numerical linear algebra
batched dense linear algebra
0.312018
Autotuning Numerical Dense Linear Algebra for Batched Computation With GPU Hardware Accelerators · Proc. IEEE 2018
High-performance computing
numerical linear algebra
0.312018
Autotuning Numerical Dense Linear Algebra for Batched Computation With GPU Hardware Accelerators · Proc. IEEE 2018
High-performance computing › performance optimization
auto-tuning
0.112018
Autotuning Numerical Dense Linear Algebra for Batched Computation With GPU Hardware Accelerators · Proc. IEEE 2018
GPUs and heterogeneous computing
GPU computing
0.112018
Autotuning Numerical Dense Linear Algebra for Batched Computation With GPU Hardware Accelerators · Proc. IEEE 2018
High-performance computing
performance engineering
0.112018
Autotuning Numerical Dense Linear Algebra for Batched Computation With GPU Hardware Accelerators · Proc. IEEE 2018

Methods — techniques the papers use, named apart from their topics

cholesky factorization · 0.3auto-tuning · 0.3
YearPublicationVenuePosition
2019 Massively Parallel Automated Software Tuning
abstract
This article presents an implementation of a distributed autotuning engine developed as part of the Bench-testing OpenN Software Autotuning Infrastructure project. The system is geared towards performance optimization of computational kernels for graphics processing units, and allows for the deployment of vast autotuning sweeps to massively parallel machines. The software implements dynamic work scheduling to distributed-memory resources and takes advantage of multithreading for parallel compilation and dispatches kernel launches to multiple accelerators. This paper lays out the main design principles of the system and discusses the basic mechanics of the initial implementation. Preliminary performance results are presented, encountered challenges are discussed, and the future directions are outlined.
Jakub Kurzak, Yaohung M. Tsai, Mark Gates, Ahmad Abdelfattah, Jack J. Dongarra
ICPP2
2018 Autotuning Numerical Dense Linear Algebra for Batched Computation With GPU Hardware Accelerators
abstract
Computational problems in engineering and scientific disciplines often rely on the solution of many instances of small systems of linear equations, which are called batched solves. In this paper, we focus on the important variants of both batch Cholesky factorization and subsequent substitution. The former requires the linear system matrices to be symmetric positive definite (SPD). We describe the implementation and automated performance engineering of these kernels that implement the factorization and the two substitutions. Our target platforms are graphics processing units (GPUs), which over the past decade have become an attractive high-performance computing (HPC) target for solvers of linear systems of equations. Due to their throughput-oriented design, GPUs exhibit the highest processing rates among the available processors. However, without careful design and coding, this speed is mostly restricted to large matrix sizes. We show an automated exploration of the implementation space as well as a new data layout for the batched class of SPD solvers. Our tests involve the solution of many thousands of linear SPD systems of exactly the same size. The primary focus of our techniques is on the individual matrices in the batch that have dimensions ranging from 5-by-5 up to 100-by-100. We compare our autotuned solvers against the state-of-the-art solvers such as those provided through NVIDIA channels and publicly available in the optimized MAGMA library. The observed performance is competitive and many times superior for many practical cases. The advantage of the presented methodology lies in achieving these results in a portable manner across matrix storage formats and GPU hardware architecture platforms.
Jack J. Dongarra, Mark Gates, Jakub Kurzak, Piotr Luszczek, Yaohung M. Tsai
Proc. IEEE5
2014 Adaptive block size for dense QR factorization in hybrid CPU-GPU systems via statistical modeling
Ray-Bing Chen, Yaohung M. Tsai, Weichung Wang
Parallel Comput.2