Silicon photonic devices are essential components of integrated optical communication systems and emerging photonic processors. However, their performance is notably impacted by fabrication-process variations (FPVs), which primarily stem from optical lithography imperfections. The impact of FPVs can accumulate and deteriorate the system-level performance through, for example, increasing system power consumption, accumulated crosstalk noise, and degrading signal integrity in photonic systems. In this paper, we discuss the promise of variation-aware design-space exploration and optimization to enhance photonic device robustness under different FPVs while considering two silicon photonic devices used widely in different applications, namely Microring Resonators (MRRs) and Mach-Zehnder Interferometers (MZIs). In addition, we consider a system-level case study of an MZI-based coherent neural network, where we show how our proposed variation-aware design optimization at the device level helps improve the network accuracy by up to 88% under FPVs.

Silicon photonics promises revolutionary advancements in communication and computing, leveraging the integration of photonic components onto silicon platforms. However, a critical challenge remains in achieving robust device performance under inevitable process variations inherent in CMOS fabrication. Existing design methodologies often fall short in assessing and mitigating the impact of these variations on device behavior, particularly in microring resonators (MRRs). To address this challenge, we present a novel, comprehensive workflow for designing process-variation-resilient silicon photonic MRRs, which we have integrated into a variation-aware design optimization framework called process variation analysis tool. Our approach seamlessly integrates process-variation robustness directly into the design phase, enabling early optimization of device performance characteristics. By exploring diverse process-variation scenarios, our workflow provides crucial insights into design tradeoffs and strategies for enhancing MRR robustness. Furthermore, we achieve this analysis efficiently through the use of compact models, striking a balance between accuracy and computational cost. This approach significantly reduces design cycles and resource requirements, offering a practical and cost-effective path toward optimizing MRR performance under real-world manufacturing conditions.

Silicon photonic microring resonators (MRRs) offer many advantages (e.g., compactness) and are often considered as the fundamental building block in optical interconnects and emerging photonic nanoprocessors and accelerators. Such devices are, however, sensitive to inevitable fabrication-process variations (FPVs) stemming from optical lithography imperfections. Consequently, silicon photonic integrated circuits (PICs) integrating MRRs often suffer from high power overhead required to compensate for the impact of FPVs on MRRs and, hence, realizing a reliable operation. On the other hand, the design space of MRRs is complex, including several correlated design parameters, thereby further exacerbating the design optimization of MRRs under FPVs. In this article, we present, for the first time, a comprehensive design-space exploration in passive and active MRRs under FPVs. In addition, we present design optimization in MRRs under FPVs while considering different performance metrics, such as tolerance to FPVs, quality factor, and 3-dB bandwidth in MRRs. Simulation and fabrication results obtained by measuring multiple fabricated MRRs designed using our design-space exploration demonstrate a significant 70% improvement on average in the MRRs’ tolerance to different FPVs. Furthermore, we apply the proposed design optimization to a case study of a wavelength-selective MRR-based demultiplexer, where we show considerable channel-spacing accuracy within 0.5 nm even when the MRRs are placed 500$\mu \text{m}$apart on a chip. Such improvements indicate the efficiency of the proposed design-space exploration and optimization to enable power-efficient and variation-resilient PICs and optical interconnects integrating MRRs.

Domain-specific neural network accelerators have seen growing interest in recent years due to their improved energy efficiency and performance compared to CPUs and GPUs. In this paper, we propose a novel cross-layer optimized neural network accelerator called CrossLight that leverages silicon photonics. CrossLight includes device-level engineering for resilience to process variations and thermal crosstalk, circuit-level tuning enhancements for inference latency reduction, and architecture-level optimizations to enable better resolution, energy-efficiency, and throughput. On average, CrossLight offers 9.5x lower energy-per-bit and 15.9x higher performance-per-watt than state-of-the-art photonic deep learning accelerators.

Domain specific neural network accelerators have garnered attention because of their improved energy efficiency and inference performance compared to CPUs and GPUs. Such accelerators are thus well suited for resource-constrained embedded systems. However, mapping sophisticated neural network models on these accelerators still entails significant energy and memory consumption, along with high inference time overhead. Binarized neural networks (BNNs), which utilize single-bit weights, represent an efficient way to implement and deploy neural network models on accelerators. In this paper, we present a novel optical-domain BNN accelerator, named ROBIN , which intelligently integrates heterogeneous microring resonator optical devices with complementary capabilities to efficiently implement the key functionalities in BNNs. We perform detailed fabrication-process variation analyses at the optical device level, explore efficient corrective tuning for these devices, and integrate circuit-level optimization to counter thermal variations. As a result, our proposed ROBIN architecture possesses the desirable traits of being robust, energy-efficient, low latency, and high throughput, when executing BNN models. Our analysis shows that ROBIN can outperform the best-known optical BNN accelerators and many electronic accelerators. Specifically, our energy-efficient ROBIN design exhibits energy-per-bit values that are ∼4 × lower than electronic BNN accelerators and ∼933 × lower than a recently proposed photonic BNN accelerator, while a performance-efficient ROBIN design shows ∼3 × and ∼25 × better performance than electronic and photonic BNN accelerators, respectively.

The approximate computing paradigm advocates for relaxing accuracy goals in applications to improve energy-efficiency and performance. Recently, this paradigm has been explored to improve the energy-efficiency of silicon photonic networks-on-chip (PNoCs). Silicon photonic interconnects suffer from high power dissipation because of laser sources, which generate carrier wavelengths, and tuning power required for regulating photonic devices under different uncertainties. In this article, we propose a framework called AppRoXimation framework for On-chip photonic Networks (ARXON) to reduce such power dissipation overhead by enabling intelligent and aggressive approximation during communication over silicon photonic links in PNoCs. Our framework reduces laser and tuning-power overhead while intelligently approximating communication, such that application output quality is not distorted beyond an acceptable limit. Simulation results show that our framework can achieve up to 56.4% lower laser power consumption and up to 23.8% better energy-efficiency than the best-known prior work on approximate communication with silicon photonic interconnects and for the same application output quality.

With the ever growing complexity of high-performance computing (HPC) systems to satisfy emerging application requirements (e.g., high memory bandwidth requirement for machine learning applications), the performance bottleneck in such systems has moved from being computation-centric to be more communication-centric. Silicon photonic interconnection networks have been proposed to address the aggressive communication requirements in HPC systems, to realize higher bandwidth, lower latency, and better energy efficiency. There have been many successful efforts on developing silicon photonic devices, integrated circuits, and architectures for HPC systems. Moreover, many efforts have been made to address and mitigate the impact of different challenges (e.g., fabrication process and thermal variations) in silicon photonic interconnects. However, most of these efforts have focused only on a single design layer in the system design space (e.g., device, circuit or architecture level). Therefore, there is often a gap between what a design technique can improve in one layer, and what it might impair in another one. In this paper, we discuss the promise of cross-layer design methodologies for HPC systems integrating silicon photonic interconnects. In particular, we discuss how such cross-layer design solutions based on cooperatively designing and exchanging design objectives among different system design layers can help achieve the best possible performance when integrating silicon photonics into HPC systems.

Microring resonators (MRRs) are very often considered as the primary building block in silicon photonic integrated circuits (PICs). Despite many advantages, MRRs are considerably sensitive to fabrication non-uniformity (a.k.a. fabrication process variations), necessitating the use of power-hungry compensation methods (e.g., thermal tuning) to guarantee their reliable operation. Moreover, the design space of MRRs is complicated and includes several highly correlated design parameters, preventing designers from easily exploring and optimizing the design of MRRs against fabrication process variations (FPVs). In this paper, for the first time, we present a comprehensive design space exploration and optimization of MRRs against FPVs. In particular, we indicate how physical design parameters in MRRs can be optimized during design time to enhance their tolerance to FPVs while also improving the insertion loss and quality factor in such devices. Fabrication results obtained by measuring multiple fabricated MRRs designed using our design optimization solution demonstrate a significant 70% improvement on average in MRRs tolerance to different FPVs. Such improvement indicates the efficiency of our novel design optimization solution in reducing the tuning power required for reliable operation of MRRs.

The approximate computing paradigm advocates for relaxing accuracy goals in applications to improve energy-efficiency and performance. Recently, this paradigm has been explored to improve the energy efficiency of silicon photonic networks-on-chip (PNoCs). In this paper, we propose a novel framework (LORAX) to enable more aggressive approximation during communication over silicon photonic links in PNoCs. This is the first work that considers loss-aware laser power management and multilevel signaling to enable effective data approximation and energy-efficiency in PNoCs. Simulation results show that our framework can achieve up to 31.4% lower laser power consumption and up to 12.2% better energy efficiency than the best known prior work on approximate communication in PNoCs, for the same application output quality.