This paper presents a bootstrapped switch with an accelerated gate-voltage rising speed and a reduced on- resistance for high-speed ADCs. Compared to the classic bootstrapped switch, this design accelerates the rising speed of gate voltage through four novel techniques. First, an extra NMOS transistor is added to pull up the gate voltage by injecting extra charges into the gate node. Second, the parasitic capacitance at the gate node is reduced by simplifying the circuit structure, leading to a faster speed. Third, transmission gates are used to reduce the two delays to one delay. Fourth, the voltage stored on the capacitor is increased to slightly larger than VDD, which leads to a faster gate-voltage rising speed as well as a larger value of gate voltage (about Vn+1.05 VDD). The larger gate voltage also helps reduce the on-resistance of the bootstrapped switch, which is helpful for the high-speed sampling of ADCs. In a 40 nm CMOS process, post-layout simulation results show that the rising speed of gate voltage is increased by 3.3 times compared to the classic thin-oxide bootstrapped switch circuit. And the on-resistance of the bootstrapped switch is reduced by 2.2 times compared to the classic structure, due to the larger gate voltage value.

A high-speed comparator constituted by a backgate-input latch and a pre-amplifier is proposed in this paper. Instead of using extra input transistors as in a classic StrongARM latch, the back-gate-input technique proposed in this paper obviates the need for extra input transistors in the latch stage, thus greatly reducing the parasitic capacitance and improving the comparator speed. Unlike the StrongARM latch where the amplification phase begins only after the CLK rises, the amplification phase in this paper begins before the CLK rises and replaces the reset phase, further improving the comparator speed. The pre-amplifier provides a gain of 22-dB, in order to suppress the input-referred noise and offset of the comparator. Designed in the same 22nm Silicon-on-Insulator (SOI) CMOS process for the proposed comparator and the conventional comparators, post-layout simulation results show that the performance in speed and input-referred noise are improved by 22% and 43%, respectively.

This brief presents a novel timing mismatch background calibration algorithm for time-interleaved (TI) analog-to-digital converters (ADCs). It can calibrate an arbitrary number of channels with an arbitrary input frequency. It also increases the calibration accuracy by applying the autocorrelation functions with an expanded interval. Besides, the proposed algorithm effectively prevents the small derivative values in the correlation difference from degrading the skew estimation accuracy. Compared to prior works on calibration, this work has at least five times better detection accuracy when the frequency of the input signal is close to the Nyquist frequency. This is without the need for calculating the high-order statistics. Finally, we simulate a four-channel 12-bit TI ADC with non-ideal effects added. Simulation results show that the proposed algorithm increases the signal to noise-plus-distortion ratio (SNDR) and spurious-free dynamic range (SFDR) from 35.5 and 40.0 dB to 63.3 and 84.6 dB, respectively, when the input frequency is close to the Nyquist frequency.

This brief presents a three-stage comparator and its modified version to improve the speed and reduce the kickback noise. Compared to the traditional two-stage comparators, the three-stage comparator in this work has an extra amplification stage, which enlarges the voltage gain and increases the speed. Unlike the traditional two-stage structure that uses pMOS input pair in the regeneration stage, the three-stage comparator makes it possible to use nMOS input pairs in both the regeneration stage and the amplification stage, further increasing the speed. Furthermore, in the proposed modified version of three-stage comparator, a CMOS input pair is adopted at the amplification stage. This greatly reduces the kickback noise by canceling out the nMOS kickback through the pMOS kickback. It also adds an extra signal path in the regeneration stage, which helps increase the speed further. For easy comparison, both the conventional two-stage and the proposed three-stage comparators are implemented in the same 130-nm CMOS process. Measured results show that the modified version of three-stage comparator improves the speed by 32%, and decreases the kickback noise by ten times. This improvement is not at the cost of increased input referred offset or noise.

This paper proposes a low-power low-cost on-chip digital background calibration for a pipelined ADC. This new redundant-stage calibration algorithm reduces the effect of quantization noise and can be applied for multiple stages; hence, it improves the calibration accuracy and is easily implemented fully on-chip with low power and low hardware cost. We realize the proposed calibration technique in a prototype 12-bit 250-MS/s pipelined ADC fabricated in a 55-nm technology. The measured results show that the prototype ADC, with an active area of 1310 μm × 510 μm, achieves an signal-to-noise-and-distortion ratio of 66.7 dB [effective number of bits (ENOB) = 10.8 bit] and consumes a total power of 85 mW with a sampling rate of 250 MS/s after applying our digital calibration, where the on-chip digital calibration circuit consumes only 5 mW and an active area of 360 μm × 510 μm.

This article presents a novel pico-watt voltage reference (VR) circuit whose power consumption is well controlled at high temperature. Unlike a traditional pico-watt VR circuit whose power consumption increases exponentially with temperature, the power consumption in this article increases linearly with temperature, thus saving much energy at high temperature. It generates the reference voltage through a 2-transistor (2-T) structure and a current generator to well control the current versus temperature. In the current generator, a gate leakage transistor replaces a huge resistor, thus saving 4-mm2area. Fabricated in a 0.13-$\mu \text{m}$CMOS process, this VR circuit generates a reference voltage of about 560 mV and shows an average temperature coefficient (TC) of 18.4 ppm/°C after trimming across −25 °C to 85 °C and a line sensitivity (LS) of 0.15%/V, while consuming 20 pW at 1-V${V} _{\text {DD}}$and 27 °C. The power consumption at 3.3-V${V} _{\text {DD}}$and 85 °C is 114 pW, which is at least two times smaller than reported in state-of-the-art work at high temperature. The core area is 0.003 mm2.

A novel voltage comparator, termed an edge-race comparator (ERC), is proposed in this article. It compares the differential input voltage by generating two propagating edges in two inverter loops and by measuring the distance between the two edges. The two edges race with each other and the winner is finally determined. The comparator is low power and low noise and does not require high-voltage headroom. It can automatically adjust its noise, power consumption, and delay according to the input voltage, thereby saving significant energy and time in coarse comparisons and reducing the noise in fine comparisons (noise averaging is performed over a longer time in fine comparisons). It is well suited for low-power, high-resolution successive approximation register (SAR) analog-to-digital converters (ADCs) (SAR ADCs). Compared to a recently published edge-pursuit comparator (EPC), the proposed structure achieves 3.39 times faster speed at 1-mV input by using a novel configuration of two inverter loops with a distance measurement circuit. The energy consumption per comparison is reduced by 2.73 times at 1-mV input owing to the shorter required comparison time. Designed in a standard 40-nm CMOS process, the measurement results from an ADC show that the comparator energy at the LSB is reduced by 7.5 times, and the ADC sampling rate is increased by 3.85 times.

This paper proposes a low-power low-cost on-chip digital background calibration for a pipelined ADC. This new redundant-stage calibration algorithm reduces the effect of quantization noise and can be applied for multiple stages; hence, it improves the calibration accuracy and is easily implemented fully on-chip with low power and low hardware cost. We realize the proposed calibration technique in a prototype 12-bit 250-MS/s pipelined ADC fabricated in a 55-nm technology. The measured results show that the prototype ADC, with an active area of 1310 gm × 510 gm, achieves an signal-to-noise-and-distortion ratio of 66.7 dB [effective number of bits (ENOB) = 10.8 bit] and consumes a total power of 85 mW with a sampling rate of 250 MS/s after applying our digital calibration, where the on-chip digital calibration circuit consumes only 5 mW and an active area of 360 gm × 510 gm.