!Non-binary low density parity check (NB-LDPC) codes are known to have higher correction capability than their binary counterparts, low density parity check (LDPC) codes. The latest technique for analyzing NB-LDPC codes is to measure generalized girth. The generalized girth cannot be measured in a binary LDPC code, and can be considered an indicator for measuring the performance of NB-LDPC code. In this paper, we propose a new analysis method to represent NB-LDPC code as a graph. This graph is called a permutation graph. In this paper, we present and prove a reasoning for analyzing generalized girth using the permutation graph. This is a faster and simpler method than the existing generalized girth analysis method. The proposed code construction algorithm constructs NB-LDPC codes to have an arbitrary generalized girth length. Because the permutation graph-based analysis is applied, which is more effective than existing methods, the complexity of code construction is significantly reduced. This enables more efficient code construction. The decoding simulations show that the proposed method improves the correction performance of NB-LDPC codes compared to the existing state-of-the-art.

In this paper, a new ECC (error correcting code) solution for DRAM (dynamic random access memory) in computing systems is proposed. Existing papers on ECC for DRAM systems do not consider storage space for metadata. The methodology proposed in this paper considers storing metadata attached to a cacheline data in DRAM. We infer the maximum number of single-chip error correction cases that a linear code can support while considering metadata storage space. This can be said to be the maximum theoretical correction probability for a single chip error. A methodology to construct a code with maximum single-chip error correction is presented. A decoding methodology for the code is proposed. The proposed ECC solution can correct not only single chip failure but also additional small bit errors. We calculate the correction capability of the proposed methodology and verified it through simulation. The encoder and decoder hardware were synthesized and compared with existing methodologies.

Although the near threshold voltage (NTV) design has achieved energy efficiency, certain challenges remain regarding its application. In this paper, we describe the analysis of thermally induced reliability concern in test process. In an NTV environment, the thermal dependency of a circuit delay is changed, and a difference in thermal constraints from that in a nominal voltage design exists. In addition, we propose a new test scheduling method for NTV circuits that alleviates the thermal constraints in system-on-chip test processes. Our simulation results show that the test time could be reduced while minimizing the reliability loss.

The 3-D integrated dynamic random-access memory (DRAM) structure with a processor is being widely studied due to advantages, such as a large band-width and data communication power reduction. In these structures, the massive heat generation of the processor results in a high operating temperature and a high refresh rate of the DRAM. Thus, in the 3-D DRAM over processor architecture, temperature-aware refresh management is necessary. However, temperature determination is difficult, because in the 3-D DRAM, the temperature changes dynamically and temperature variation in a DRAM die is complicated. In this paper, a thermal guard-band set-up method for 3-D stacked DRAM is proposed. It considers the latency of the temperature data and the position difference between the temperature sensor and the DRAM cell. With this method, the data reliability of the on-chip temperature sensor-dependent adaptive refresh control is guaranteed. In addition, an efficient temperature sensor built-in and refresh control method is analyzed. The expected refresh power reduction is examined through a simulation.