This article proposes a probability-driven intercolumn error cancellation mechanism for approximate multiplier design, enabling an improved tradeoff between computational accuracy and hardware efficiency. By statistically characterizing the error behavior of approximate compressors and coordinating positive and negative error units, effective column-level error cancellation is achieved. Asubarray truncation strategy is further integrated into a recursive multiplier architecture to reduce partial product generation and accumulation overhead. Multiple approximate multipliers with different accuracy levels are implemented and synthesized in a 28-nm CMOS process. Compared with an exact$8{\,}\times{\,} 8$multiplier, the high-accuracy ECM8-1 achieves near-lossless accuracy while reducing the power–area–delay product (PADP) by 35.6%, whereas the low-power ECM-TT22 achieves a reduction of up to 99.6%. In image processing applications, the high-accuracy and low-power designs achieve 99.8% and above 85.4% Structural Similarity Index (SSIM) in blurring, and 99.6% and 84.9% SSIM in edge detection, respectively. In quantized deep neural networks (DNNs) inference workloads, ECM8 incurs less than 0.3% accuracy loss on CIFAR-10, while ECM-O and ECM-T maintain near-exact performance on MNIST, demonstrating robustness across different precision levels and suitability for hardware-efficient DNN acceleration.

Goal-oriented visual dialogue involves multi-round interaction between artificial agents, which has been of remarkable attention due to its wide applications. Given a visual scene, this task occurs when a Questioner asks an action-oriented question and an Answerer responds with the intent of letting the Questioner know the correct action to take. The quality of questions affects the accuracy and efficiency of the target search progress. However, existing methods lack a clear strategy to guide the generation of questions, resulting in the randomness in the search process and inconvergent results. We propose a Tree-Structured Strategy with Answer Distribution Estimator (TSADE) which guides the question generation by excluding half of the current candidate objects in each round. The above process is implemented by maximizing a binary reward inspired by the ``divide-and-conquer'' paradigm. We further design a candidate-minimization reward which encourages the model to narrow down the scope of candidate objects toward the end of the dialogue. We experimentally demonstrate that our method can enable the agents to achieve high task-oriented accuracy with fewer repeating questions and rounds compared to traditional ergodic question generation approaches. Qualitative results further show that TSADE facilitates agents to generate higher-quality questions.

With the rapid growth of Internet of Things (IoT) applications, ensuring the data privacy and security has become a critical concern. The security of integrated circuits (ICs) in IoT systems is of paramount importance. As IC integration increases, circuit testing becomes increasingly challenging. Design For Testability (DFT) techniques improve testability, but scan-based methods can be easily exploited by unauthorized users to steal confidential information. For this reason, researchers have proposed various defense techniques, but each technique has its limitations. In order to effectively protect the scan chains of ICs from illegal access, this paper presents a novel DFT framework based on hidden, randomly inserted key seeds and Physical Unclonable Function (PUF). A multiple-input shift register is used as a test key generator, which receives the hidden test key seed from randomly selected scan chains, and then generates a unique key for each test pattern. An authentication module is also introduced to verify the validity of the test patterns. Through key verification, if a test vector contains valid key seed, the design will perform normal scan operations. Conversely, if the seed hidden in a test vector cannot generate the expected test key, the scan output data will be scrambled by the random PUF responses, thereby effectively preventing attackers from inferring sensitive information. Theoretical analysis and experimental results show that the proposed secure DFT protects the cryptographic chip from all known scan-based side-channel attacks, while requiring no additional test preparation time and incurring only negligible low area overhead.

By integrating memristors into a Hopfield neural network (HNN), a diverse range of dynamical behavior can be generated, which has significant implications for modeling and biomimetic applications of artificial neurons. However, research on the firing dynamics of HNNs remains relatively limited. In response, a memristive tri-neurons Hopfield neural network (MTN-HNN) was constructed, with the synapse of the second neuron replaced by the proposed memristor. A theoretical and experimental investigation of the dynamics of this neural network was conducted using general analytical tools, such as phase diagrams, Lyapunov exponents, bifurcation diagrams, and others. Experimental results indicate that the dynamics of the MTN-HNN is influenced by the internal parameters of the memristor, enabling the network to extend attractors in up to two directions and thereby form grid multi-scrolls. Notably, the MTN-HNN exhibits various firing modes, including periodic and chaotic bursting. Finally, an encryption scheme was proposed to demonstrate the potential of the MTN-HNN, and both the custom digital circuits and the encryption scheme were successfully implemented on a Field-Programmable Gate Array (FPGA).

Transistor sizing and spacing are constantly decreasing due to the continuous advancement of CMOS technology. The charge of the sensitive nodes in the static random access memory (SRAM) cell gradually decreases, making the SRAM cell more and more sensitive to soft errors, such as single-node upsets (SNUs) and double-node upsets (DNUs). Therefore, two types of radiation-hardened SRAM cells are proposed in this article. First, a low-power DNU self-recovery S6P8N cell is proposed. This cell can realize SNU self-recovery from all sensitive nodes as well as realize partial DNUs self-recovery and has low-power consumption overhead. Second, we propose a high-speed DNU self-recovery S8P6N cell, which has a soft-error tolerance level similar to the S6P8N. Furthermore, it reduces the read access time (RAT) and write access time (WAT). Simulation results show that the proposed cells are self-recovery for all SNUs and most of DNUs. Compared with RHD12, QCCM12T, QUCCE12T, RHMD10T, SEA14T, RHM-12T, S4P8N, S8P4N, RH-14T, HRLP16T, CC18T, and RHM, the average power consumption of S6P8N is reduced by 48.78%, and the average WAT is reduced by 6.62%. While the average power consumption of S8P6N is reduced by 23.64%, and the average WAT and RAT by 9.07% and 36.84%, respectively.

As CMOS process sizes continue to shrink, static randomized memory (SRAM) cells have become very sensitive to the charge generated by high-energy radiation particles, making them more susceptible to Single Event Upsets(SEUs). In this paper, a highly reliable and low-power radiation hardened 20T SRAM (RH-20T) cell is proposed. RH-20T is able to recover from single-node upsets (SNU) at all sensitive nodes, and also the structure has ten node pairs for self-recovery from double-node upsets(DNU). Simulation results demonstrate its advantages in terms of reliability and power consumption over typical existing radiation-hardened SRAM cell designs, such as ZHANG14T, QUCCE12T, RHMD10T, SEA14T, SCCS, S4P8N, S8P4N, DNUSRM, SESRS and CC18T, the RH-20T achieves an average power consumption reduction of 44.61%, and an average write access time (WAT) reduction of 19.78%.

The data privacy and security of Internet of Things (IoT) applications are progressively crucial and cryptography is frequently used to ensure security. Cryptographic hardware implementation is commonly adopted for high throughput and low-computational resources. The crypto circuits have to be strictly tested to guarantee the correctness of data. Scan-based design-for-testability (DFT) widely employed in the chip industry improves the controllability and observability of circuits. However, it facilitates illegal users to steal the internal data for cracking cryptographic keys. Many researchers have recently suggested effective defense technologies against scan-based attacks, but each technology has its own negative aspects. In this article, we propose an effective DFT authorization framework (DAF) based on obfuscation mechanisms. The authentication module is embedded to verify users’ keys, and it can empower each chip distinctive key to minimize the loss of key divulgence. If the test authorization key is accurate, the typical scan operation can be carried out. Conversely, if the key is inaccurate, the inserted obfuscation module comes into play to scramble the scan data. Additionally, a random number generation circuit is used to increase the uncertainty of data obfuscation, effectively preventing attackers from inferring sensitive information. Simulation results show that this design has a low overhead, and theoretical analysis demonstrates that the design has high security with no impact on the testability of the chip.

With the continuous shrinking of the size of the semiconductor process, the multi-node upset (MNU) brought about by the charge-sharing effect in the nano-integrated circuit has a huge impact on the reliability of the chip. In this paper, a low-delay quadruple-node-upset self-recoverable (LDQNUSR) latch is proposed, which employs seven identical multi-level soft-error interception modules (SIM), each of which is composed of six two-input C-element (CEs) and an inverter. Due to the error interception characteristics of each SIM and the mutual feedback mechanism, this latch has complete quadruple-node-upset (QNU) self-recovery capabilities. Simulation results show that the proposed latch can tolerate all QNUs and can self-recover from any QNUs. In addition, latch overhead can be reduced due to the use of high-speed transmission gates and clock gating techniques. The proposed latch has lower delay compared to the latest LDAVPM latch.

Autonomous vehicle (AV) evaluation has been the subject of increased interest in recent years both in industry and in academia. This paper focuses on the development of a novel framework for generating adversarial driving behavior of background vehicle interfering against the AV to expose effective and rational risky events. Specifically, the adversarial behavior is learned by a reinforcement learning (RL) approach incorporated with the cumulative prospect theory (CPT) which allows representation of human risk cognition. Then, the extended version of deep deterministic policy gradient (DDPG) technique is proposed for training the adversarial policy while ensuring training stability as the CPT action-value function is leveraged. A comparative case study regarding the cut-in scenario is conducted on a high fidelity Hardware-in-the-Loop (HiL) platform and the results demonstrate the adversarial effectiveness to infer the weakness of the tested AV.

Cryptography chips are often used in some applications, such as smart grids and Internet of Things (IoT) to ensure their security. Cryptographic chips must be strictly tested to guarantee the correctness of the encryption and decryption. Scan-based design-for-testability (DFT) provides high test quality. However, it can also be misused to steal the cipher key of cryptographic chips by hackers. In this article, we present a new scan design methodology that can resist scan-based side-channel attacks by the dynamical obfuscation of scan input data and scan output data. The scan test is managed by a test password, which consists of load password and scan password. When the chip enters into the test mode, it is required to apply the test password via some external input ports. Once the correct load password is delivered, the scan password can be loaded into a special shift register. If the scan password is also correct, the chip testing can proceed normally. In case the load password or the scan password is wrong, the data in scan chains cannot be propagated correctly. Specifically, some elusory bits are sneaked into scan chains dynamically. The advantage of the proposed method is that it has no negative impact on design performance and test flow when powerfully protecting cryptographic chips. The area penalty is also acceptably low compared with other schemes.

With the continuous progress of semiconductor processes, the multiple-node upset (MNU) caused by radiation has become a major problem affecting chip reliability. To tolerate MNU, a low-cost quadruple-node-upset self-recoverable (LCQNUSR) latch is proposed in this paper, mainly consisting of six inverters and six four-input C-element (CEs), which are cross-connected to form a feedback loop. The latch make full use of the fault-tolerance property of the CEs to constitute a multilevel filtering mechanism, so that the latch provides complete quadruple-node-upset (QNU) self-recovery capability. Simulation results show that the proposed latch is not only QNU tolerant, but also self-recovering from QNU. In addition, due to the use of high-speed transmission path and clock gating techniques, the proposed latch reduces the delay-power-area product by about 88.89% compared to the latest MNU hardened latch.

As an attractive option of future non-volatile memories (NVM), resistive random access memory (RRAM) has attracted more attentions. CMOS Molecular (CMOL) architecture, which can alleviate the sneak path problem of one memristor (1R) crossbars and limit its power consumption in 1R crossbars, is used as a large-scale memory system. In this paper, we analyze the electrical defects in a CMOL circuit including open and bridge. A parallel March-like test algorithm is presented for the CMOL architecture, which covers defined faults caused by electrical defects. The test time of the proposed test algorithm is reduced significantly compared with previous test algorithms that are enhanced for CMOL architecture.