Charge-trap transistors (CTTs) are compute-in-memory devices that are used to model synaptic arrays in neuromorphic systems. CTTs enable non von Neumann architectures, thus, eliminating the energy spent on compute-memory communication. Synaptic weights can be stored in CTTs by shifting the threshold voltage of the devices in an analog manner. CTTs are, however, susceptible to unintentional de-trapping of charge over time due to threshold voltage instability, leading to loss of the stored synaptic weights. The proposed weight refresh system performs statistical refresh of the CTT array to replenish the charge of individual CTT devices (restore synaptic weights) based on characterization of threshold voltage instability in high-k dielectrics.

In this work, a novel digital leaky integrate-and-fire neuron design is proposed as part of a charge-trap transistor (CTT)-based neuromorphic system. CTTs, which are compute-in-memory devices, are used to realize the synaptic array of the neuron and support weight multiplication operations for incoming pulse signals. The proposed digital neuron does not rely on a capacitor for accumulation, making it area-efficient and scalable, and thus useful for design of large spiking neural networks. The neuron accumulates the weighted inputs from the synaptic array and generates an outgoing pulse, i.e., fires, when a pre-set threshold is reached. The digital neuron includes a sampler circuit, multi-level comparator, pulse generator, leaky circuit, 3-bit counter, and digital comparator circuit. Since the circuit is digital, the design is robust to noise, mismatch, and process, voltage, and temperature variations. The digital neuron is designed in GF 22 nm FDSOI technology, operates at a supply voltage of 0.8 V, and occupies an area of 33.5 μ m2. The neuron was simulated, including under temperature and supply voltage variations, and exhibits expected functionality.

This paper presents an ultra-wideband (UWB) transmitter based on capacitive array that decreases dependency of data rate to pulse repetition frequency, as well as power consumption and complexity. The entire system includes several delay stages, a capacitive array circuit, a Schmitt trigger, an impulse generator, a cross-coupled oscillator, and an antenna driver. A sequence of 5-bit parallel data is applied to the capacitive array, providing ramp signals with 32 equally separated slopes. This returns a variable pulsewidth at the output of the Schmitt trigger circuit, which corresponds to a specific sequence of input data. Post-layout simulation results show that the proposed circuit provides a linear time change in the pulsewidth with an accuracy of 176 ps in average for every input data LSB. Furthermore, the entire circuit consumes only 190 µW from a 0.6-V supply. The proposed transmitter achieves a significantly low energy consumption of 950 fJ/bit at 200 Mbps within the Federal Communications Commission spectral mask which addresses the design challenges of ultralow-power internet-of-things devices. The circuit is designed in TSMC 65-nm standard CMOS technology and occupies 0.0525 mm2of die area.

This paper presents a tunable new deadtime control circuit providing an optimal delay for power converter optimization. Our method can reduce the deadtime loss while improving the efficiency and power density of a given power converter. The circuit presents a reconfigurable delay element to generate a wide range of deadtime for different power conversion applications with varying loads and input voltages. The optimal deadtime equation for buck converters is derived, and its dependency on the input voltage and load is discussed. Experimental results show that the presented circuit can provide a wide range of deadtime delays, ranging from 9.2 ns to 1000 ns. The power consumption of the presented circuit is measured for different capacitive loads ($\text{C}_{\mathrm {L}}$) and operating frequencies (${f}_{\mathrm {s}}$). The circuit consumed a power between 610$\mu \text{W}$and$850~\mu \text{W}$across the measured deadtime ranges while$\text{C}_{\mathrm {L}} =12$pF,$\text{V}_{\mathrm {dd}} =3.3$V, and$\text{f}_{\mathrm {s}}=200$kHz. The proposed deadtime generator can operate up to 18 MHz when the minimum deadtime of 9.2 ns is selected. The presented circuit occupies an area of$150\mu $m$\times 260\mu \text{m}$. The fabricated chip is connected to a buck converter to validate the operation of the proposed circuit. The efficiency of a typical buck converter with minimum$\text{T}_{\mathrm {DLH}}$and optimal$\text{T}_{\mathrm {DHL}}$at$\text{I}_{\mathrm {Load}} =25$mA is improved by 12% compared to a converter with a fixed deadtime of$\text{T}_{\mathrm {DLH}} =\,\,\text{T}_{\mathrm {DHL}} =12$ns.

In this study, a dead-time control circuit is proposed to generate independent delays for the high and low sides of half-bridge converter switches. In addition to greatly decreasing the losses of power converters, the proposed method mitigates the shoot-through current through the application of superimposed power switches. The circuit presented here comprises a switched capacitor architecture and is implemented in AMS 0.35$\mu \text{m}$technology. In the implementation, the proposed dead-time control circuit occupies a silicon area of$70\,\,\mu \text{m}\,\,\times 180\,\,\mu \text{m}$. To realize the technique, a two-sided wide swing current source is employed. Each sides of the current source comes with two capacitors, two Schmitt triggers, and three transmission gates. Results show that the low and high sides of the projected half-bridge converter switches respectively require delays of 35 and 62 ns. The performance of the proposed dead-time circuit is evaluated by assembling it with the half-bridge converter. The proposed dead-time prototype achieves a 40% drop in power losses in the half-bridge circuit.

A novel level down shifter intended for translation of signals with different amplitudes in System-on-Chip (SoC) applications is presented. This new single supply down-shifter architecture, implemented in a 0.35μm AMS CMOS technology provides multiple reconfigurable levels. A diode connected circuit structure, a current source, five transmission gates, a diode- supercapacitor combination, and input/output buffers are employed to implement this reconfigurable level shifter. The circuit receives a pulse shaped signal with an amplitude of 3.3 V, and provides three different signals with nominal amplitudes of 1.2 V, 1.8 V, and 2.5 V depends on the circuit configuration. The proposed circuit successfully drives a range of capacitive loads between 10 fF and 350 pF. The presented circuit consumes a static and a dynamic power consumptions of 62.37 pW and 108μW, respectively from a 3.3V supply, at an operating frequency of 1 MHz and a capacitive load of 10 pF. Post-layout simulation results show that the fall and rise propagation delays of the three configurations are in the range of 0.54 ns-26.5 ns and 11.2 ns-117.2 ns, respectively. It occupies an area of 80 μmx100 μm.

A novel non-overlapping signal generator intended for power-converters operation is presented. This switched capacitor circuit architecture-based sensor and actuator interface is implemented in AMS-H35B4D3 technology and consumes a power of 51.8 mW from a 3.3V-supply at 1 Mbps. Two-sided wide swing current source, two capacitors, Schmitt triggers and three transmission gates are employed on each side of the current source for implementing this versatile building block. The circuit provides needed dead-time to the power amplifier for high and low voltage applications. The time period of the master CLK is 1μs. The proposed circuit successfully generates two outputs with 0.4813 μs (~half of period) non-overlapping delay between the phases. It occupies an area of 70 μm×180 μm from the total half bridge area of 800 μm×1370 μm.