Shengping Lv

dblp:146/1946 · DBLP profile ↗
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7ranked-venue papers
5as first author
6since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 3 · 2 first-author · 3 since 2021Systems, architecture and hardware · 3 · 2 first-author · 3 since 2021Computer networks · 1 · 1 first-author
YearPublicationVenuePosition
2026 A 40 μV VRipple, 0.1-ps FoM Output-Capacitor-Less Fully Time-Domain Digital LDO With a VCO-Assisted Dual Loop
Guanzhe Hu, Shengping Lv, Wen Jia, Shuqiang Lu, Hanjun Jiang
ISCAS2
2026 A Low Noise Bio-potential AFE Achieving 300-mV EDO Tolerance and <20-ms-Settling with VCO-based Full Digital DC Servo Loop
Shengping Lv, Guanzhe Hu, Liuxin Lv, Fei Chen 0006, Wen Jia, Shuqiang Lu, Zhihua Wang 0001, Hanjun Jiang
ISCAS1
2026 Q-learning-guided local search in NSGA-III for multi-objective flexible job shop scheduling with dual-resource and parallel batch processing
Shengping Lv, Zhuohui Li, Jiayi Wei
Expert Syst. Appl.1
2025 A lightweight hierarchical aggregation task alignment network for industrial surface defect detection
Shengping Lv, Tairan Liang, Kaibin Zhang, Shixin Jiang, Bin Ouyang, Quanzhou Li
Expert Syst. Appl.1
2025 A genetic algorithm enhanced with neighborhood structure for general flexible job shop scheduling with parallel batch processing machine
Hucheng Zhang, Shengping Lv, Dequan Xin
Expert Syst. Appl.2
2024 A Capacitor-Less LDO Regulator Compensated by Adaptive Zero for Zero-Load Stability Enhancement
abstract
A flipped voltage follower (FVF)-based capacitor-less low-dropout (LDO) regulator is presented that features a fast transient response. The adaptive zero compensation is proposed to solve the full-load-range stability issue associated with the FVF LDO regulator. The presented FVF LDO regulator has been implemented in a 0.18 μm CMOS process with an active area of 0.026 mm2. The simulated loop phase margin exceeds 45° for the entire load range of 0-40 mA. The minimum power supply rejection of 56 dB at 1 MHz has been measured at the maximum load current of 40 mA. The measured transient response time is 0.48 ns over the load current range with a dynamic quiescent current of 36 to 76 μA, which results in a figure of merit among the best reported in recent publications.
Shengping Lv, Peiyuan Wan, Liuxin Lv, Hanjun Jiang
ISCAS1
2020 Establishing Secrecy Region for Directional Modulation Scheme with Random Frequency Diverse Array
abstract
Random frequency diverse array (RFDA) based directional modulation (DM) was proposed as a promising technology in secure communications to achieve a precise transmission of confidential messages, and artificial noise (AN) was considered as an important helper in RFDA-DM. Compared with previous works that only focus on the spot of the desired receiver, in this work, we investigate a secrecy region around the desired receiver, that is, a specific range and angle resolution around the desired receiver. Firstly, the minimum number of antennas and the bandwidth needed to achieve a secrecy region are derived. Moreover, based on the lower bound of the secrecy capacity in RFDA-DM-AN scheme, we investigate the performance impact of AN on the secrecy capacity. From this work, we conclude that: 1) AN is not always beneficial to the secure transmission. Specifically, when the number of antennas is sufficiently large and the transmit power is smaller than a specified value, AN will reduce secrecy capacity due to the consumption of limited transmit power. 2) Increasing bandwidth will enlarge the set for randomly allocating frequencies and thus lead to a higher secrecy capacity. 3) The minimum number of antennas increases as the predefined secrecy transmission rate increases.
Shengping Lv, Jinsong Hu 0001, Youjia Chen, Zhimeng Xu 0001, Zhizhang (David) Chen
GLOBECOM1