The Cascaded H-bridge energy storage converter (CHBESC) integrates energy storage components within cascaded multilevel converters to deliver short-term high power to the stator of ultra-high-speed linear motors. This integration effectively mitigates the impact on the power grid. However, during the acceleration and braking of the ultra-high-speed linear motor, the frequency of the CHBESC output voltage varies with the motor speed. This variation causes the frequency of secondary harmonic currents in the submodules to fluctuate accordingly. To address this issue, this paper establishes an analytical model for secondary harmonic voltage and current over a wide frequency range. The study investigates the fluctuation patterns of these harmonics under different control and circuit parameters, providing theoretical guidance for the design of circuit parameters and controllers. Simulation results validate the accuracy of the model and the effectiveness of the parameter design guidance.

Low switching frequency of power semiconductor devices is expected to decrease losses in the cascaded H-bridge (CHB) inverter with supercapacitor and dc–dc stage. This paper proposes a switching frequency reduction method accompanied by a hybrid modulation strategy (HMS) for the CHB inverter. By optimizing the comparison output between the reference wave and the triangular carrier, unnecessary state jumps in the switching signals for the H-bridge can be avoided when rotating the switching mode of the H-bridge in the HMS. The proposed method can reduce the average switching frequency among the H-bridges without side effects on capacitor voltage balance and ac outputs. Finally, its effectiveness is demonstrated through simulation results of five SMs based on MATLAB/Simulink.

Hardware-in-the-loop (HIL) real-time simulation of cascaded H-bridge inverter (CHBI) with supercapacitor and DC-DC stage is one of the important links in the development of its controller. This paper presents a full-scale HIL simulator for the CHBI. Firstly, the discrete mathematical model of the CHBI is derived and implemented by utilizing several field programmable gate arrays (FPGAs) as the solving units. Each FPGA is equipped with up to twelve fiber optic communication interfaces, allowing one-to-one connection between the simulator and its controller. The simulation capacity of the presented simulator can be easily expanded through incorporating more FPGAs and combining data communication. Finally, the effectiveness of the presented simulator for the CHBI is verified through the gridconnected charging HIL real-time simulation results.

Cascaded H-bridge with bidirectional DC-DC converter (CHBDC) is promising in high voltage supercapacitor (SC) energy storage applications, in terms of multilevel voltage output, modularity, high efficiency, etc. However, the charging process becomes complicated when part of the SC voltages reach the target value ahead of the others. The improper charging may cause the CHBDC over-modulation and even grid current distortion. To solve this problem, this paper analyzes the stable operation area of the CHBDC in this scenario. Based on these analysis, a coordinated charging strategy is also proposed for the CHBDC, by adjusting the reference voltage of each H-bridge unit and the grid power factor. Simulation results show the validity of the proposed charging strategy.