Frequent and inconsistent main-memory requests in large-scale Network-on-Chip (NoC) systems pose significant performance challenges. While strategies like multi-level cache hierarchies and network resource optimization mitigate memory bottlenecks, their impact on the statistical predictability of memory access remains underexplored.We propose a structured methodology to guide the design of NoC-based systems by balancing the tradeoff between the statistical predictability of memory access and the average throughput of the memory controller (MC). Using Power Spectral Density (PSD) of inter-packet arrival times (IPAT) at MC, we evaluate the impact of key architectural parameters, cache size, buffer size, and network size on memory access predictability. We analyze changes in PSD characteristics, including stationarity, monofractal chaos, and multifractal chaos, alongside average MC throughput to identify optimal parameter values that maximize both predictability and throughput. Our results demonstrate that fine-tuning these parameters can alleviate chaoticity in IPAT at MC, thereby providing a valuable framework for designing efficient NoC-based systems across diverse applications.

Most complex cooperative systems, such as networks on chip (NoCs), possess self-organizing properties and exhibit fluctuations in data traffic with similar statistical characteristics across multiple timescales, a.k.a., scaling behavior. Abrupt transitions in the scaling behavior of these fluctuations, caused by spikes in data traffic, network congestion, etc., indicate instability in the queueing dynamics of NoC routers. This instability hampers the predictability of real-time flow control mechanisms, leading to unpredictable delays and communication failures. Detecting and mitigating these instabilities or phase transitions is crucial in domains requiring stability and real-time control, such as aviation and healthcare. In this paper, we propose a real-time monitoring and characterization strategy for data traffic from influential routers to identify and mitigate impending instabilities before their onset. Leveraging the self-organization characteristic of NoCs, we propose to implement targeted mitigation on influential nodes to achieve network-wide effects. We demonstrate the effectiveness of our strategy on various benchmarks by comparing traffic analysis plots before and after mitigation. Our results show that the proposed phase transition mitigation improves the network performance by an average of 39.6% and buffer utilization by an average of 4.62%.

Increasing complexity in power management (PMT) has led to a growing demand for third-party power managers (3PPMs) in Network-on-Chip based Mixed-Critical Systems (NoCMCS). However, a malicious 3PPM can exploit the interdependence of power amongst the router nodes to orchestrate well-structured, covert power attacks. Detection and localization of a malicious 3PPM is crucial to restore standard dynamic PMT and mitigating system performance degradation. We propose a novel, non-invasive, low-overhead, attack detection and localization framework for Hardware Trojan (HT)-assisted intermittent power attacks with random activation and deactivation phases in NoCMCS. In Phase-I, our framework makes use of pre-profiled thermal statistics of router nodes to detect any anomaly at runtime. In Phase-II, it leverages a self-aware methodology to locate the router nodes with malicious 3PPM. The proposed framework can detect multiple intermittent HTs in the network. Experimental evaluations on real-life benchmarks show that Phase-I of our framework is able to consolidate the search space of malicious nodes, reducing almost 90% of Phase-II’s computational workload. Phase-II localizes the malicious router nodes across various experimental scenarios with zero false positives. We also demonstrate the robustness of our framework for detecting and localizing malicious router nodes for different intermittent HTs with varying burst attacks over time.

Modern Multi-Processor-Systems-on-Chips (MPSoCs) use Network-on-Chips (NoCs) as a scalable and efficient communication fabric. The applications running on these devices rely on frequent communication with central database servers, which are vulnerable to impersonation attacks by adversarial clones. We propose NoCiPUF, a novel NoC-based intrinsic Physically-Unclonable-Function (PUF) framework for MPSoCs authentication. We re-use the circuit switched nature of NoC with path-pairs as challenges to obtain secret responses, collectively called challenge-response-pairs (CRPs). Due to the random nature of manufacturing variations, equal hop paths exhibit unequal delays. We leverage the delay differences of flits traversing in equal-hop paths to generate unique responses. NoCiPUF is fully-synthesizable and readily scalable as it requires changes only at the behavioral level. To counter Machine-Learning (ML)-based modeling attacks on PUFs, we provide a comprehensive technique and reduce the prediction accuracy to ~52%. NoCiPUF framework incurs low area (0.76%) and power (1.14%) overheads and has no impact on NoC performance in normal mode due to independent authentication mode. Obtained responses have near-ideal PUF metrics and are verified against the NIST randomness test suite. This scheme offers high number of CRPs in larger NoC networks ($>0.74$million CRPs in 5×5 mesh), proving its scalability.