Open Radio Access Network (O-RAN) provides the capability to efficiently distribute the RAN Network Functions (NFs) such as the Radio Unit (RU), Distributed Unit (DU) and Centralized Unit (CU) in O-RAN Cloud (O-Cloud) nodes using virtualization, automation, intelligence and open interface specifications. In addition, Carrier Aggregation (CA) technology enhances the throughput of the users by aggregating Component Carriers (CCs) and allocating one Primary Cell (PCell) and multiple Secondary Cells (SCell) to each user. Finding the DU NFs placement of each CC (PCell or SCell) while minimizing the number of used O-Cloud nodes and the average user end to end delay is our aim in this paper. Thus, we model the average delay and propose an algorithm using Deep Q Network (DQN) based Deep Reinforcement Learning (DRL) algorithm to find the solution to the problem. Simulation results demonstrate that our proposed scheme reduces the average end user delay and the number of employed O-Cloud nodes at least 90% and 20% with respect to the baselines.

In this paper, a probabilistic analysis of the cycle distribution of protograph-based spatially coupled low-density parity-check (SC LDPC) codes is presented. In particular, we derive the probability that cycles of specific, but arbitrary, length are broken as a result of spatial coupling with a random spreading matrix in a general edge spreading process. Our results show that the probability of existence of cycles in SC codes is O(1/m), where m is the code memory. This result is independent of the cycle length.

In this paper, we propose a design technique for the construction of variable-regular time-invariant spatially-coupled low-density parity-check (SC-LDPC) codes with small constraint length and low error floor. The proposed technique reduces the error floor by imposing simple constraints on the short cycles in the code's Tanner graph, which in turn, result in the elimination of the most dominant trapping sets of the code. In some cases, we also derive lower bounds on the syndrome former memory for satisfying such constraints. The designed codes are superior to the state-of-the-art in terms of error floor performance and/or decoding complexity and latency.