We introduce a novel soft-decision decoding algorithm for binary block codes named ordered reliability direct error pattern testing (ORDEPT). The proposed technique tests a list of partial error patterns (PEP)s that are arranged according to their logistic weight and completed on-the-fly based on the instantaneous received sequence and the code’s parity-check matrix. Our results, obtained for a variety of popular short high-rate codes, demonstrate that ORDEPT outperforms state-of-the-art decoding algorithms such as ordered reliability bits guessing random additive noise decoding (ORBGRAND) in terms of decoding complexity, and is hardware-favorable in terms of latency and energy consumption. The improvements carry on to the iterative decoding of product codes and convolutional product-like codes, where ORDEPT demonstrates the ability to efficiently find multiple candidate codewords and outperform state-of-the art competitors.

This brief presents a power and memory-optimized hardware implementation for the open forward error correction (oFEC) encoder proposed for high-speed fiber optical communications. Instead of storing a large amount of previously encoded data in the memory as suggested in oFEC proposal, we propose an alternative algorithm that requires the knowledge of only a few blocks of preencoded partial parity-check bits with the goal to reduce circuit power consumption. We then present a hardware implementation architecture for both the standard and optimized encoding algorithms and demonstrate that power dissipation and area overhead are reduced multiple times by optimized implementation.

We focus on a hardware implementation of the concatenated forward error-correction (FEC) decoder defined in 400ZR implementation agreement to provide a throughput of 400 Gbps over fiber-optical communication links. We propose a soft-input hard-output low-complexity decoding algorithm for the inner Hamming code. We demonstrate that the algorithm leads to an efficient hardware design with low silicon area and power dissipation. We then propose a hardware implementation architecture of the outer staircase decoder. It features a highly optimized low-power implementation of Bose-Chaudhuri-Hocquenghem (BCH) component decoders and the staircase decoder memory that can be efficiently accessed by either vertical or horizontal component decoders. Finally, we analyze the hardware implementation of the entire 400ZR decoder and investigate the trade-off in terms of power, area, and speed, that results from the inner/outer decoder concatenation and is dictated by the bit-error rate at the output of the inner decoder.

The paper describes the design of a differential broadband LNA covering the frequency range from 800 MHz to 5 GHz in 65nm CMOS technology. The work proposes a novel linearization technique for high-frequency wide-band applications using an active feedback as post-distortion. The technique is applied to a wide-band differential common gate (CG) LNA employing noise cancellation method. Post-layout simulations exhibit that the proposed technique increases IIP3 and P1dB considerably to +11.9 and +1 dBm, respectively at 1.8 GHz. The LNA achieves voltage gain of 13.7-13.9 dB, noise figure of 3-3.28 dB, and S11 less than -10 dB, while consuming only 16.5 mW. The layout schematic occupies 0.515 × 0.220 mm2of chip area.