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T. S. Bindiya

dblp:148/1420 · DBLP profile ↗
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6ranked-venue papers
2as first author
2since 2021 · last 2025
0000-0002-8406-1833ORCID · verified

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 since 2021Applied, interdisciplinary, general and emerging computing · 2Artificial intelligence and machine learning · 1 · 1 first-authorDatabases, data management, data science and information retrieval · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 100%
Artificial intelligence
1 paper
Deep learning architectures and training · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
activation function implementation
0.712023
Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Hardware accelerators and domain-specific architectures › machine learning accelerator › neural network accelerator
LSTM accelerator
0.712023
Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Hardware accelerators and domain-specific architectures
machine learning accelerator
0.712023
Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Machine learning › Deep learning architectures and training › recurrent neural network
LSTM
0.212023
Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
Machine learning › Deep learning architectures and training
recurrent neural network
0.212023
Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2023
YearPublicationVenuePosition
2025 Modeling of Izhikevich Spiking Neurons With High Matching Accuracy Using Comb-Exp Functions and Its Multiplier-Free Realization
abstract
In the realm of neuroprosthetics, the imperative for hardware-efficient, faster spiking neuron models, reproducing spiking patterns with better precision, has emerged as a pivotal necessity; catalyzing advancements towards more compact and resource-optimal solutions for seamless integration within neural prosthetic systems. In this brief, a new digital model for Izhikevich Spiking neuron is proposed. The model accurately replicates the spiking patterns and phase portraits corresponding to the neuronal dynamic behaviour with a very high matching between the original and proposed models, high speed and improved hardware efficiency. The results of synthesis on the field programmable gate array (FPGA) platform demonstrate that the proposed hardware gives significant improvements in resource consumption and maximum operating frequency when compared to the latest existing Izhikevich spiking neuron architectures. A digit classification system using the proposed SNN model is implemented to demonstrate its applicability. Polychronous neuronal groups, which are ideal for signal-processing tasks like language learning and object recognition, are also simulated using the proposed model, which is significant in neuroprosthetic applications.
P. V. Sruthi, T. S. Bindiya
IEEE Trans. Circuits Syst. I Regul. Pap.2
2023 Realization and Hardware Implementation of Gating Units for Long Short-Term Memory Network Using Hyperbolic Sine Functions
abstract
This article proposes a new activation function (AF)$\mathrm {sinh}(\beta x) + \mathrm {sinh}^{-1}(\beta x)$called combined hyperbolic Sine (comb-H-sine) to replace existing AFS like$\sigma $and$\tanh $in long short-term memory (LSTM) neural networks. The comb-H-sine function is implemented using purely combinational architectures with a 16-bit data width with fixed-point representation, resulting in improved accuracy. Both software and hardware modeling are used to investigate the proposed architecture. Compared to prior works on$\sigma $and$\tanh $functions, the hardware for the comb-H-sine function shows significant improvements in power consumption, number of cells, cell area, and delay. The proposed LSTM architecture using comb-H-sine outperforms existing AFs in terms of power delay product and accuracy on various datasets.
Tresa Joseph, T. S. Bindiya
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2019 A New Multiplier-free Transformation for the Design of Hardware Efficient Circularly Symmetric Wideband 2D Filters
abstract
In this paper, a new multiplier-free transformation is proposed for the design of low complexity two dimensional (2D) finite impulse response (FIR) filters with improved circularity at wideband radii. By designing the 1D filter multiplier-free and using proposed multiplier-free transformation, a 2D circularly symmetric multiplier-free filter can be realized. Accuracy of the circular contour is measured based on contour approximation error. To prove the hardware efficiency of the proposed transformation, a 2D band-pass filter and a low-pass filter are designed and the overall complexity in terms of the number of multipliers required to implement the 2D filters is compared. From the results it is clear that the proposed transformation have good circularity at wideband radii and have less implementation complexity.
K. R. Sreelekha, T. S. Bindiya
TENCON2
2019 Design and Implementation of Maximally Decimated Polyphase Filter Bank for Power and Delay Efficient Digital Hearing Aids
abstract
A computationally efficient maximally decimated filter bank core, suitable for digital hearing aids is designed and implemented in this work. The main advantages of the proposed design method are that the computational complexity and delay are less than that of the other filter bank based architectures in the literature. To reduce the hardware complexity of the filter bank core, filter coefficients are optimized and are implemented multiplier-free.
Sudhi Sudharman, T. S. Bindiya
TENCON2
2016 Meta-heuristic evolutionary algorithms for the design of optimal multiplier-less recombination filter banks
T. S. Bindiya, Elizabeth Elias
Inf. Sci.1
2014 Metaheuristic algorithms for the design of multiplier-less non-uniform filter banks based on frequency response masking
T. S. Bindiya, Elizabeth Elias
Soft Comput.1