The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

Today, testing of AMS circuits needs to improve quality towards ppb test escape levels as well as decrease the test development time to reduce the IC lead time. A defect-oriented solution can improve quality by focusing on structural tests that can detect defects more efficiently than traditional functional tests, while test reuse can decrease test development time on ICs built with reusable IP blocks. A defect-oriented built-in self-test (BIST) approach integrates both solutions. This paper proposes a test development methodology for analog IP blocks based on such defect-oriented BIST framework. The methodology allows for achieving the target defect coverage at the lowest possible cost. Co-designing the IP with the DfT structures allows accounting for any non-idealities that the DfT may add to the IP. Test structures cost is limited by using low-cost signal generation and a new output response analyzer (ORA). The proposed methodology is demonstrated on two case studies. The results show that coverages higher than 90% are possible using a simple digital pulse signal and an ORA with only 4 bits of accuracy, while coverages higher than 95% are possible with 6 bits, offering a good trade-off between coverage and cost.

In industry-scale integrated circuit (IC) production, continuous improvements in processing and testing have resulted in defect test escape rates gradually reaching levels below 100 PPB for analog and mixed-signal (AMS) ICs. Newer methodologies are needed to reduce these rates even further in light of the ever-tightening reliability requirements in the automotive industry while minimizing additional costs. Detecting latent defects is a major challenge today. A research experiment was conducted to assess and improve the latent defect test escape rate of industry-scale AMS testing at test time. This experiment altered the IC production process to artificially introduce latent gate oxide defects of different sizes and locations in a commercially available automotive IC in a 350-nm high-voltage BCD process currently in production. The standard industrial test program was able to detect 58.4% of the latent defects at a yield loss of 6.2%. The latent defect detection rate has been improved to 95.5% at an additional yield loss of only 0.8% using support vector machine (SVM) classifiers on the dataset of measurements resulting from the standard test program. This type of classifier is chosen for its optimal use of available data. The results show that a significant gain in coverage is possible without adding extra tests. In the experiment, testing at high temperatures (HOT) proved crucial in achieving this coverage benefit. Furthermore, while traditional tests mainly detect latent defects close to the source of transistors, the SVM approach significantly improves the detection of pinhole latent defects closer to the drain.

Electronics employed in modern safety-critical systems require severe qualification during the manufacturing process and in the field, to prevent fault effects from manifesting themselves as critical failures during mission operations. Traditional fault models are not sufficient anymore to guarantee the required quality levels for chips utilized in mission-critical applications. The research community and industry have been investigating new test approaches such as device-aware test, cell-aware test, path-delay test, and even test methodologies based on the analysis of manufacturing data to move the scope from OPPM to OPPB. This special session presents four contributions, from academic researchers and industry professionals, to enable better chip quality. We present results on various activities towards this objective, including device-aware test, software-based self-test, and memory test.

With quality and reliability requirements moving toward the ppb level, latent defects have become a major bottleneck. This article introduces a new metric, called difference in the distance to mean value (DDtM), that exploits the latent defect information present in measurements of an integrated circuit (IC) carried out under more than one operating condition. The use of this metric improves the latent defect coverage provided by post-processing (PP) techniques at no additional cost. The DDtM tracks, for each measured variable, shift in the distance from the IC’s measured value to the population mean value when the conditions applied to the IC change. To demonstrate the effectiveness of the DDtM metric, two circuits that are part of an industrial mixed-signal IC are used as case studies. The results show that the use of the DDtM metric improves latent defect coverage regardless of the PP technique used, providing up to a 60% improvement in coverage compared to the results obtained using the same measurement data but without DDtM.

In this work, a novel outlier detection method is presented in which the data from the visual inspection of manufactured wafers are combined with the data from the electrical test. Three different implementations are built with increasing complexity in order to detect outliers that are not detected by a traditional outlier detection method such as the Dynamic Part Average Testing (DPAT). The screening parameters are constructed as a reformulation of the DPAT formulas, integrating information from visual inspection and the layout of the used product. The proposed VEDPAT algorithms are applied to a total of 25 wafers spread over 5 lots in order to compare their effectiveness. The results show that a method that combines the available information with the layout is able to effectively screen out outliers at the expense of only a very small yield loss. Also, details and microscope pictures of the false alarms and outliers detected by the method are presented.

With tightening automotive IC production test requirements, test escape rates need to decrease down to the 10 PPB level. To achieve this for mixed-signal ICs, advanced multivariate statistical techniques are needed, as the defects in the test escapes become increasingly more difficult to detect. Therefore, this paper proposes applying a cascade of advanced statistical techniques to identify measurements that can be used as predictors to flag future potential failures at test time with minimal misclassification of good devices. The approach uses measurement data from the ATE wafer probe tests and is also able to identify the likely location of the defect using only these measurements. The cascade has four steps: 1) remove bias and spatial patterns within the data, 2) divide the different tests into relevant groups, 3) reduce the dimensionality of each group, and 4) perform multiple regression to find the predictor values and use these values to compute an outlier score for each chip under test. As there is a risk of overfitting the outlier score, the number of predictors used is kept to a minimum. The effectiveness of the proposed methodology is demonstrated using test data from an industrial production chip with eight field-return cases. Predictors have been found that retroactively allowed the identification of these chips, with an average of 5% false classification of good devices, i.e. devices not returned from the field. In addition, the selected predictors corresponded to where the defects are located according to failure analysis of the field returns.

Automotive applications are driving the need for better IC quality, reliability, and functional safety, in a market that is cost-sensitive and rapidly changing. The goals are to deliver zero defective parts without time-consuming and expensive burn-in, and satisfy functional safety requirements. This paper shows how measuring the percentage of circuit elements that are subject to sufficient stress during testing, especially across thin oxides, can be used as a criterion to drive improving the circuit's reliability. The paper also shows how to more accurately compute a circuit's ISO 26262 metrics using activity-based defect likelihoods. Simulation results are provided for an ITC'17 mixed-signal benchmark circuit (bandgap + LDO + voltage monitor) and for an industrial automotive product IC, showing the potential of the method to improve reliability and functional safety of analog/mixed-signal ICs.

Test detection of lifetime failures due to latent defects is a necessity to reach the tightening quality requirements of automotive systems. This paper presents a pinhole latent defect model, together with a simulation workflow, that can be used to develop defect-oriented analog test approaches for pinhole latent defects. This work also defines the latent defect coverage and activation coverage, providing the means to compare different test methods under the same rules. Furthermore, a circuit taken from an industrial mixed-signal IC is used as case study. The results show that the typically applied specification tests are insufficient to detect latent defects. It is demonstrated that the coverage can be increased by adding well-selected tests in combination with voltage stress techniques. Doing so, the coverage for the case study is increased by 15x.

Safety-critical and mission-critical systems, such as airplanes or (semi-)autonomous cars, are relying on an ever-increasing number of embedded integrated circuits. Consequently, there is a need for complete defect coverage during the testing of these circuits to guarantee their functionality in the field. In this context, reducing the escape rate of defects during production testing is crucial, and significant progress has been made to this end. However, production testing using automatic test equipment is subject to various measurement parasitic variations, which may have a negative impact on the testing procedure and therefore limit the final defect coverage. To tackle this issue, this article proposes an improved test flow targeting increased analog defect coverage, both at the system and block levels, by analyzing and improving the coverage of typical functional and structural tests under these measurement variations. To illustrate the flow, the technique of inserting a pseudo-random signal at available circuit nodes and applying machine learning techniques to its response is presented. A DC-DC converter, derived from an industrial product, is used as a case study to validate the flow. In short, results show that system-level tests for the converter suffer strongly from the measurement variations and are limited to just under 80% coverage, even when applying the proposed test flow. Block-level testing, however, can achieve only 70% fault coverage without improvements but is able to consistently achieve 98% of fault coverage at a cost of at most 2% yield loss with the proposed machine learning–based boosting technique.

The test and design methodology currently used to develop automotive mixed-signal integrated circuits, is not sufficient to achieve the <; 10 PPB quality target. In particular it does not allow to activate and detect all latent defects, which are a significant cause of vehicle failures in the field. This paper discusses whether full burn-in will be needed in order to meet the quality goal, or whether Vstress in combination with a defect activation coverage methodology will do the job.

Guaranteeing correct and reliable cyber-physical systems requires testing of analog/mixed-signal ICs towards low defect escape rates, below the ppm level. It also requires guaranteeing correct functioning over the product lifetime. However, there are not yet industry-wide automated tools that can generate adequate tests to this end for analog/mixed-signal ICs, like it is currently the case with digital ICs. This paper presents different methods and algorithms that target decreasing defect test escapes in analog/mixed-signal ICs. These methods are based on structural testing for defects, they use fault analysis tools for escape rate analysis and employ DfT structures to increase test coverage, which reduces test escape rate. Furthermore, these structures activate possible latent defect, that may pose threats during the lifetime of integrated circuits.

The quality level of the analog parts in mixed-signal ICs lags behind the below-part-per-million escape rates of the digital core. The reason is that analog blocks in these ICs have high test escape rates as a result of the typical testing based on performance specifications. Test point selection/insertion techniques have been proposed to solve this problem by offering increased observability. However, their effectiveness in practice is still limited due to the lack of a commonly accepted methodology to make probing of internal nodes in analog circuitry possible. This paper presents a low-cost and highly parallel DfT technique based on inserting testing diodes to internal circuit nodes, which enables those test point selection algorithms at low cost. An industrial case study demonstrates 90.4% fault coverage value with a very small overhead in area and test time.

An automatic, defect-oriented method is proposed for activating latent defects in analog and mixed-signal integrated circuits. Based on the topology modification technique, added stress transistors generate voltage stress that activates these latent defects. This contrasts with burn-in testing which uses increased temperatures as a fault activation mechanism. Moreover, this Design-for-Testability algorithm gives the trade-off between fault activation rate, silicon area cost and testing time for different test solutions. Both CMOS and DMOS devices are handled to accommodate the testing of high-voltage circuits. When applied to latent gate oxide defects in a voltage regulator circuit, an activation rate of up to 76.7% is achieved. In comparison, the stressing by increased supply voltage only reaches 28%. For the same testing time, this improvement comes at the expense of three additional stress transistors with a silicon area overhead of less than 1%.

The quality level of mixed-signal ICs lags behind the below-part-per-million defect test escape rates of digital ICs, as a result of the traditional testing based on performance specifications. Methods increasing the controllability to solve the problem of the low fault coverage of analog and mixed-signal circuits are in practice limited due to the excessive area overhead they require and their impact on the normal circuit operation. This paper presents a non-intrusive method to improve the controllability using light as an activation mechanism. The necessary simulation models are introduced to use the proposed method in the context of a defect-oriented test approach. This work also describes a workflow which enables the application of the method to large-scale industrial circuits. Finally, effective results are shown on an industrial mixed-signal front-end circuit under test (CUT) demonstrating around 27% increase in the number of detectable defects.

A method is presented to address the automatic generation of test signals for analog and mixed-signal integrated circuits. No restriction on the number of inputs or the nonlin-earity of the circuit are made. The circuit under consideration is first decomposed into a set of sub-circuits, called blocks, in order to break down the complexity of the problem. The effect of a targeted fault is then automatically analyzed at the transistor level in a defect-oriented context. From this analysis, the fault sensitization conditions are extracted and then backtraced towards the primary inputs and outputs of the circuit using an algorithm based on the interval analysis theory. The underlying algorithms supporting the automation of the whole procedure are illustrated for basic circuits. Finally, in order to demonstrate the method, an industrial circuit is used as case study. It is shown that test signals can be generated in order to achieve a fault coverage of 98%.

The growing number of chips in automotive applications has created an increasing urge to avoid electronic failures in the field. Part Average Testing (PAT) is a generally used technique to screen out early-life failures for automotive products. In this paper we demonstrate with industrial data the application of Dynamic Part Average Testing (DPAT) at the final testing stage in order to improve the analog fault coverage of a mixed-signal automotive product. Simulation results on an industrial circuit indicate an analog fault coverage improvement from 31.3 % to 82.7 %. This is demonstrated with experimental data.

The detection level of defects in today's mixed-signal ICs lags behind the extremely high demand of industries such as automotive. This is mainly because analog blocks in these ICs have high test escape rates as a result of the typical testing based on the performance specifications. Defect-oriented techniques have been proposed to solve the problem of this poor fault coverage for analog circuits. Their effectiveness in practice is however still limited due to the inadequate fault models used to represent physical failures. This paper presents a new open-gate DC fault model. Experimental results on fabricated test circuits in 0.35μm BCD technology are used to validate the proposed fault model and the commonly used high-value-resistance model. Finally, a new testing approach to detect the corresponding open defects in analog circuits is discussed, which is based on forcing the transistors outside their designed operation region.

In this paper a new method is presented to automatically generate a Design-for-Testability infrastructure which increases the observability of defects in integrated circuits. An algorithm is proposed to detect circuit locations to which small detection blocks can be added. Those are coupled to an oscillator and the triggering of this oscillator in case of detected defects leaves traces in the power consumption. Therefore, the detection of a defective circuit can directly be transmitted to the Automated Test Equipment without requiring a special routing of the signals on the chip and extra test pins. Simulations on an industrial circuit show a 86 percent fault coverage of the hard-to-detect faults for an area increase of less than a percent.

A general method is proposed to automatically generate a DfT solution aiming at the detection of catastrophic faults in analog and mixed-signal integrated circuits. The approach consists in modifying the topology of the circuit by pulling up (down) nodes and then probing differentiating node voltages. The method generates a set of optimal hardware implementations addressing the multi-objective problem such that the fault coverage is maximized and the silicon overhead is minimized. The new method was applied to a real-case industrial circuit, demonstrating a nearly 100 percent coverage at the expense of an area increase of about 5 percent.

A new method is presented to detect catastrophic defects from the signal analysis of dynamic current consumption waveforms of analog circuits. While other techniques use the whole information in a Root-Mean-Square computation or in black-box techniques such as a neural network, the central point of this work resides in the selection of waveform samples to create a signature able to discriminate a defective circuit from a fault-free circuit. The selection of samples is implemented by the introduction of binary vectors to partially mask the data. Confronted with process variations, this technique offers the advantage of being straightforward and simple to implement in Automated Test Equipments. The generation of the masks is optimized to improve the defect coverage by means of a genetic algorithm maximizing the distance between the signature of the fault-free circuit and a faulty circuit. Results from simulations on industrial circuits show that the number of detected defects can be nearly doubled for specific stimuli.

Electronics are increasingly being embedded in a growing number of applications in our daily life. This demands strong reliability and robustness of those electronic systems. The IC manufacturing process not being perfect, however, inevitably results in some fabricated parts having defects. Test methods must detect such faulty ICs before shipment. While the fault coverage of testing for digital integrated circuits in industry today already reaches the sub-ppm level, this is not yet the case for analog integrated circuits or the analog part in mixed-signal ICs. This invited talk will review some techniques that are being explored in industrial practice to aim for sub-ppm-level coverage for the analog and mixed-signal circuits as well. This will be illustrated with some practical examples from automotive IC designs.