Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page

Travis S. Craig

dblp:148/5126 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 1993
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Embedded and real-time systems · 62% Parallel and multicore computing · 19% Memory systems · 19%
Software engineering, system software, and programming languages
1 paper
Concurrent programming · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Concurrent programming
synchronization
0.011993
Queuing spin lock algorithms to support timing predictability · RTSS 1993
Embedded and real-time systems › real-time scheduling
timing predictability
0.011993
Queuing spin lock algorithms to support timing predictability · RTSS 1993
Memory systems › cache › multiprocessor cache
coherent cache
0.011993
Queuing spin lock algorithms to support timing predictability · RTSS 1993
Parallel and multicore computing › multiprocessor system
shared-memory multiprocessor
0.011993
Queuing spin lock algorithms to support timing predictability · RTSS 1993

Methods — techniques the papers use, named apart from their topics

atomic swap instruction · 0.0
YearPublicationVenuePosition
1993 Queuing spin lock algorithms to support timing predictability
abstract
We introduce practical new algorithms for FIFO and priority-ordered spin locks on shared-memory multiprocessors with an atomic swap instruction. Different versions of these queuing spin locks are designed for machines with coherent-cache and NUMA memory models. We discuss extensions to provide nested lock acquisition, conditional locking, timeout of lock requests, and preemption waiters. These locks support predictable timing in the lowest kernel and user levels of time-line-scheduled and priority-scheduled real-time systems.>
Travis S. Craig
RTSS1