Digitization of geographic regions, such as bodies of water, from remotely sensed imagery is a highly demanded yet arduous task. Though many automatic approaches for such digitization exist, they are typically geared towards specific regions of interest and sensing platforms, requiring complex workflow specification, parameter tuning, and/or manual training set creation. Moreover, the automatic digitization is performed all at once, making correction overwhelming when the result is not fully accurate. In this study, a general-purpose methodology that aims to greatly reduce the burden of geographic region digitization is proposed. This methodology specifies an interface for a human-machine team that exploits an incremental approach via online and active learning. With no prior training data or workflow definition, an effective pixel-level classifier is built in stride with a human user's adjustments to the machine's automatic vertex placement via novel interactive piecewise-linear contours. Several contour implementations specifically tailored towards geographic regions are presented along with results showing the effectiveness of each implementation. These contours work by spatially constraining the placement of vertices such that a machine implementation may effectively classify and train on pixel-level data for vertex placement after human verification or correction. An implementation of the methodology that uses a K nearest neighbors classifier and a simple instance-based estimation of uncertainty is presented along with several automatic vertex insertaion and placement strategies. Results show that the presented implementation succeeds in helping the user effectively annotate with no prior training data, yielding a vertex placement accuracy of 84% overall. Finally, conclusions and current research directions initiated from our findings are discussed.

Multisocket computer systems are popular in workstations and servers. However, they suffer from the relatively low bandwidth of intersocket communication especially for massive parallel workloads that generate many intersocket requests for synchronizations and remote memory accesses. Intersocket traffic puts pressure on the underlying network connecting all processors with a limited bandwidth confined by pin resources. Given this constraint, we propose to dynamically increase the intersocket bandwidth by sacrificing off-chip memory bandwidth when systems have heavy intersocket communication but few off-chip memory accesses. Our design increases the physical bandwidth for intersocket communication via switching the function of pins from off-chip memory accesses to intersocket communication and can achieve an average performance speedup of 1.28 in geocentric mean for selected parallel multithreaded benchmarks.

Snapshot Isolation (SI) is an established model in the database community, which permits write-read conflicts to pass and aborts transactions only on write-write conflicts. With the Write Skew anomaly correctly eliminated, SI can reduce the occurrence of aborts, save the work done by transactions, and greatly benefit long transactions involving complex data structures.

Off-chip memory bandwidth has been considered as one of the major limiting factors of processor performance, especially for multi-cores and many-cores. Conventional processor design allocates a large portion of off-chip pins to deliver power, leaving a small number of pins for processor signal communication. We observe that a processor requires much less power during memory intensive stages than is available. This is due to the fact that the frequencies of processor cores waiting for data to be fetched from offchip memories can be scaled down in order to save power without degrading performance. Motivated by this observation, we propose a dynamic pin switching technique to alleviate this bandwidth limitation. This technique is introduced to dynamically exploit surplus power delivery pins to provide extra bandwidth during memory intensive program phases, thereby significantly boosting performance. This work is extended to compare two approaches for increasing off chip bandwidths using switchable pins. Additionally, it shows significant performance improvements for memory intensive workloads on a memory subsystem using Phase Change Memory.

Off-chip memory bandwidth has been considered as one of the major limiting factors to processor performance, especially for multi-cores and many-cores. Conventional processor design allocates a large portion of off-chip pins to deliver power, leaving a small number of pins for processor signal communication. We observed that the processor requires much less power than that can be supplied during memory intensive stages. This is due to the fact that the frequencies of processor cores waiting for data to be fetched from off-chip memories can be scaled down in order to save power without degrading performance. In this work, motivated by this observation, we propose a dynamic pin switch technique to alleviate the bandwidth limitation issue. The technique is introduced to dynamically exploit the surplus pins for power delivery in the memory intensive phases and uses them to provide extra bandwidth for the program executions, thus significantly boosting the performance.