Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from EDBT 2026 / reviewers in the wild / expert

Marko Magerl

dblp:149/0422 · DBLP profile ↗
← Back
1ranked-venue papers
1as first author
0since 2021 · last 2016
0000-0003-4091-5320ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › design representation
behavioral modeling		 0.212016
Echo State Networks for Black-Box Modeling of Integrated Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016
Electronic design automation
circuit simulation		 0.212016
Echo State Networks for Black-Box Modeling of Integrated Circuits · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2016

Methods — techniques the papers use, named apart from their topics

reservoir computing · 0.2echo state network · 0.2
YearPublicationVenuePosition
2016 Echo State Networks for Black-Box Modeling of Integrated Circuits
abstract
A black-box method for modeling the time-domain response of integrated circuits (ICs) based on echo state networks is proposed. The number and value of the input and feedback delays required for modeling nonlinear systems with memory are detected automatically, and the training procedure is very fast and robust. The resulting models can be implemented in any hardware description language. The proposed modeling approach is applied to three test cases that cover a wide range of analog behavior. The achieved accuracy is comparable to the reference modeling method, and, depending on the complexity of the modeled IC, the simulation speed-up factor is in the order between 10 and 100.
Marko Magerl, Vladimir Ceperic, Adrijan Baric
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1