While vision-language models (VLMs) excel at tasks involving single images or short videos, they still struggle with Long Video Question Answering (LVQA) due to its demand for complex multi-step temporal reasoning. Vanilla approaches, which simply sample frames uniformly and feed them to a VLM along with the question, incur significant token overhead. This forces aggressive downsampling of long videos, causing models to miss fine-grained visual structure, subtle event transitions, and key temporal cues. Recent works attempt to overcome these limitations through heuristic approaches; however, they lack explicit mechanisms for encoding temporal relationships and fail to provide any formal guarantees that the sampled context actually encodes the compositional or causal logic required by the question. To address these foundational gaps, we introduce NeuS-QA, a training-free, plug-and-play neuro-symbolic pipeline for LVQA. NeuS-QA first translates a natural language question into a logic specification that models the temporal relationship between frame-level events. Next, we construct a video automaton to model the video's frame-by-frame event progression, and finally employ model checking to compare the automaton against the specification to identify all video segments that satisfy the question's logical requirements. Only these logic-verified segments are submitted to the VLM, thus improving interpretability, reducing hallucinations, and enabling compositional reasoning without modifying or fine-tuning the model. Experiments on the LongVideoBench and CinePile benchmarks show that NeuS-QA significantly improves performance by over 10%, particularly on questions involving event ordering, causality, and multi-step reasoning.

Recent advancements in text-to-video models such as Sora, Gen-3, MovieGen, and CogVideoX are pushing the boundaries of synthetic video generation, with adoption seen in fields like robotics, autonomous driving, and entertainment. As these models become prevalent, various metrics and benchmarks have emerged to evaluate the quality of the generated videos. However, these metrics emphasize visual quality and smoothness, neglecting temporal fidelity and text-to-video alignment, which are crucial for safety-critical applications. To address this gap, we introduce NeuS-V, a novel synthetic video evaluation metric that rigorously assesses text-to-video alignment using neuro-symbolic formal verification techniques. Our approach first converts the prompt into a formally defined Temporal Logic (TL) specification and translates the generated video into an automaton representation. Then, it evaluates the text-to-video alignment by formally checking the video automaton against the TL specification. Furthermore, we present a dataset of temporally extended prompts to evaluate state-of-the-art video generation models against our benchmark. We find that NeuS-V demonstrates a higher correlation by over 5× with human evaluations when compared to existing metrics. Our evaluation further reveals that current video generation models perform poorly on these temporally complex prompts, highlighting the need for future work in improving text-to-video generation capabilities. We open-source our benchmark, code, and dataset at utaustin-swarmlab.github.io/neusv.

This paper presents an ion-sensitive field-effect transistor (ISFET)-based biosensor for detecting phosphatidylserine (PS), a key apoptosis marker. The sensor, featuring a silicon nitride (Si3N4) membrane functionalized with Annexin V, achieved sensitivities of 20 mV/decade for Ag/AgCl electrodes and 52 mV/decade for gold electrodes, with a limit of detection down to 10 nM. Surface modification was validated via fluorescence microscopy, showing a twofold increase in signal intensity upon PS binding. Compared to fluorescence microscopy and enzyme-linked immunosorbent assay (ELISA), which require extensive processing, the ISFET-based approach offers a rapid, label-free, and miniaturizable alternative. Optimized surface treatment enhanced performance, making it suitable for real-time apoptotic marker detection and integration into portable diagnostics.

Multiple-input translinear Elements (MITEs) employing Floating Gate (FG) transistors are crucial for low-power analog signal processing due to their multiple-input capabilities. Traditionally, FG-based MITE circuits are designed using hand calculations and physically calibrated post-fabrication. This work introduces a Verilog-A model for FG-based MITEs, derived from empirical data measured from MITE devices on 350nm CMOS process, to enable advanced pre-silicon design and validation. The model facilitates the development of MITE-based circuits capable of performing analog multiplication and division. This approach enhances the design process by enabling simulations before fabrication and contributes to more efficient and versatile low-power analog circuit designs. Further, it allows designers to validate the design despite mismatches and variations.

Analog non-volatile devices are gaining prominence in computational applications due to their potential for enhanced energy efficiency and higher density compared to conventional memory technologies. This inherent advantage positions them as a promising solution for edge devices. However, these devices are susceptible to intrinsic mismatch and variation, which can severely compromise the overall accuracy of neural networks implemented with them. Our on-chip measurements reveal that variations and mismatch can lead to a significant reduction in neural network accuracy (> 10% accuracy drop). In response to these challenges, this work introduces an innovative on-chip adaptation mechanism leveraging hot-electron injection to address the issue of mismatch and variation. Through extensive experimentation, we demonstrate that our proposed method achieves a substantial reduction in overall mismatch (standard deviation of 1.23% ). This reduction in mismatch, in turn, results in a noteworthy enhancement in the accuracy of analog neural networks. By addressing the critical issue of mismatch through on-chip adaptation, our research contributes to the development of more robust and accurate analog non-volatile device-based neural networks, paving the way for their effective deployment in edge computing and other resource-constrained applications.

Abstract We provide the solution for a fundamental problem of geometric optimization by giving a complete characterization of worst-case optimal disk coverings of rectangles: For any $$\lambda \ge 1$$ λ ≥ 1 , the critical covering area $$A^*(\lambda )$$ A ∗ ( λ ) is the minimum value for which any set of disks with total area at least $$A^*(\lambda )$$ A ∗ ( λ ) can cover a rectangle of dimensions $$\lambda \times 1$$ λ × 1 . We show that there is a threshold value $$\lambda _2 = \sqrt{\sqrt{7}/2 - 1/4} \approx 1.035797\ldots $$ λ 2 = 7 / 2 - 1 / 4 ≈ 1.035797 … , such that for $$\lambda <\lambda _2$$ λ < λ 2 the critical covering area $$A^*(\lambda )$$ A ∗ ( λ ) is $$A^*(\lambda )=3\pi \left( \frac{\lambda ^2}{16} +\frac{5}{32} + \frac{9}{256\lambda ^2}\right) $$ A ∗ ( λ ) = 3 π λ 2 16 + 5 32 + 9 256 λ 2 , and for $$\lambda \ge \lambda _2$$ λ ≥ λ 2 , the critical area is $$A^*(\lambda )=\pi (\lambda ^2+2)/4$$ A ∗ ( λ ) = π ( λ 2 + 2 ) / 4 ; these values are tight. For the special case $$\lambda =1$$ λ = 1 , i.e., for covering a unit square, the critical covering area is $$\frac{195\pi }{256}\approx 2.39301\ldots $$ 195 π 256 ≈ 2.39301 … . The proof uses a careful combination of manual and automatic analysis, demonstrating the power of the employed interval arithmetic technique.

CMOS-based Ion-Sensitive Field Effect Transistors (ISFETs) are used to measure a given media’s pH. CMOS-based ISFETs, in contrast to traditional glass electrode-based pH meters, are compact and consume lower power. However, ISFETs suffer from a mismatch in their output current due to the variations in CMOS fabrication and post-fabrication insulation steps. This mismatch can significantly impact the accuracy of the pH measurements. This work presents a Floating-Gate (FG) to reduce the mismatch in the ISFETs. By employing FG-based ISFET, the study effectively tunes its threshold voltage to calibrate against the mismatch. Fowler-Nordheim tunneling removes the charge from the floating node, which effectively increases the threshold voltage. In contrast, hot-electron injection is used to program the charge onto the FG node, decreasing the threshold voltage. The work experimentally demonstrates the programming of FG-based ISFETs by fabricating them in 0.5μm CMOS process. Moreover, the work characterizes different biasing schemes to program the FG-based ISFETs efficiently.

In recent years, programming has witnessed a shift towards using standard libraries as a black box. However, there has not been a synchronous development of tools that can help demonstrate the working of such libraries in general programs, which poses an impediment to improved learning outcomes and makes debugging exasperating. We introduce Eye, an interactive pedagogical tool that visualizes a program's execution as it runs. It demonstrates properties and usage of data structures in a general environment, thereby helping in learning, logical debugging, and code comprehension. Eye provides a comprehensive overview at each stage during run time including the execution stack and the state of data structures. The modular implementation allows for extension to other languages and modification of the graphics as desired.

This work demonstrates a Continuous-Time (CT) Ladder filter using transconductance amplifiers as an approximate delay stage implemented on a large-scale Field Programmable Analog Array (FPAA) and characterized on an SoC FPAA. We experimentally demonstrate a reprogrammable CT Analog linear-phase filter by utilizing the ladder filter delay element and Vector-Matrix Multiplication (VMM) both compiled on the SoC FPAA. Using the Ladder Filter as a programmable CT delay operation enables a traditionally difficult analog signal operation. This effort extensively models and characterizes the ladder filter delay stage in terms of its transfer function, delay tunability, power requirements, distortion, and SNR. The theoretical development is compared to experimental measurements on an SoC FPAA with programmable ladder filter delay of 2.9μs and 4.2μs for multiple input frequencies (e.g. 5kHz, 20kHz). In addition, we show that VMMs can compensate the non-idealities found in the ladder filter delay-line operation.

We provide the solution for a fundamental problem of geometric optimization by giving a complete characterization of worst-case optimal disk coverings of rectangles: For any $λ\geq 1$, the critical covering area $A^*(λ)$ is the minimum value for which any set of disks with total area at least $A^*(λ)$ can cover a rectangle of dimensions $λ\times 1$. We show that there is a threshold value $λ_2 = \sqrt{\sqrt{7}/2 - 1/4} \approx 1.035797\ldots$, such that for $λ

We present a new deep multi-state Dynamic Recurrent Neural Network (DRNN) architecture for Brain Machine Interface (BMI) applications. Our DRNN is used to predict Cartesian representation of a computer cursor movement kinematics from open-loop neural data recorded from the posterior parietal cortex (PPC) of a human subject in a BMI system. We design the algorithm to achieve a reasonable trade-off between performance and robustness, and we constrain memory usage in favor of future hardware implementation. We feed the predictions of the network back to the input to improve prediction performance and robustness. We apply a scheduled sampling approach to the model in order to solve a statistical distribution mismatch between the ground truth and predictions. Additionally, we configure a small DRNN to operate with a short history of input, reducing the required buffering of input data and number of memory accesses. This configuration lowers the expected power consumption in a neural network accelerator. Operating on wavelet-based neural features, we show that the average performance of DRNN surpasses other state-of-the-art methods in the literature on both single- and multi-day data recorded over 43 days. Results show that multi-state DRNN has the potential to model the nonlinear relationships between the neural data and kinematics for robust BMIs.

This paper presents an embedded learning algorithm, a one-layer VMM + WTA classifier, on a Large-Scale Field Programmable Analog Array (FPAA), The technique enables opportunities for embedded, ultra-low power machine learning, techniques typically considered for large servers. A VMM + WTA single, one-layer network is a universal approximator. An on-chip learning algorithm was developed to train this physical classifier. A clustering step determines the initial weight set for ideal target and background values. Null symbols are important for the algorithm and are set from midpoints of the target values. Experimental measurements are shown for this learning classifier implemented on an SoC FPAA device.

This brief investigates temperature compensation techniques for circuits and systems on a reconfigurable platform. The work demonstrates use of large-scale reconfigurable system-on-chip for reducing the variability of circuits and systems compiled on a floating gate (FG)-based field-programmable analog array (FPAA). The work presents current and voltage reference which could help in reducing the variability caused due to changes in temperature. These references are standard blocks in the Scilab/Xcos environment, which could be easily compiled on the FPAA. An FG-based current reference is then used for biasing a second-order $G_{m}-C$ bandpass filter to demonstrate the compilation and usage of these voltage/current reference in a reconfigurable fabric. The large-scale FG FPAA presented here is fabricated in 350-nm CMOS process.

We present a calibration flow for a large-scale Floating-Gate (FG) System-on-Chip (SoC) Field Programmable Analog Array (FPAA) to enable analog system design and built-in self test. We focus on calibration of the FG programming infrastructure, Digital-Analog Converters (DAC) and Analog-Digital Converters (ADC), as well as characterization of hot-electron injection parameters. This paper shows the results of a compiled Winner-Take-All (WTA) circuit on three different calibrated chips.

This paper presents a low-power speech detector on a fully reconfigurable Field Programmable Analog Array (FPAA). The entire system is designed and compiled on a FPAA fabricated in 0.35μm CMOS process. The system uses 12 parallel bank of band-pass filters to extract features. The outputs of the filter bank are used by a single layer of 12×2 Vector Matrix Multiplication (VMM) and Winner Take All (WTA). The weights are stored on the VMM using pFET floating gate transistor. The power consumption of the analog system is 155.6μW with a 2.5 V power supply. The low power consumption allows the use of such a system for portable and remote sensing applications. Further, the paper investigates the performance of the system by adding white gaussian noise to the input signal. The system has an accuracy of 99.94% when the input has a SNR of 20dB and of 74% with a SNR of 8dB.

We present a calibration flow for a large-scale floating-gate (FG) system-on-chip field programmable analog array. We focus on characterizing the FG programming infrastructure and hot-electron injection parameters, MOSFET parameters using the EKV model, and calibrating digital-analog converters and analog-digital converters. In addition, threshold voltage mismatches on FG devices due to their indirect structure are characterized using on-chip measurement techniques. The calibration results in enabling a digital approach, where a design can be programmed without having to deal with the local and global mismatches, on a reconfigurable analog system. This paper shows the results of a compiled nonlinear classifier block comprising a vector-matrix-multiplier and a winner-takes-all on three different calibrated chips.

This paper presents the assessment results of using Field Programmable Analog Arrays (FPAAs) and its concomitant design automation software, RASP Tools, in an analog graduate level course to integrate hands-on activities for learning. We describe our teaching methodology as well as experiments involving the FPAA SoC and its tool suite created for this course. We are evaluating the student satisfaction of using RASP Tools and FPAA SoCs for analog design and our blended approach to convey this material. Metrics considered are students' perception of hardware & software capabilities, self-efficacy in the core areas, and their assessment of the course methodology.

This document describes the live demonstration of FPAA Demonstration Controlled through Android-Based Device1. This demonstration requires no additional resources other than the basic resources (power plug, a table and pin wall) to be provided to each demonstration 2. The demonstration will use a Google Nexus 7 tablet and a RASP 3.0 board (most likely multiple boards), which the authors will transport. The demonstration application to interface with the board runs on the tablet, as well as laptops, to show the relevant design tools to interested users. This application could be downloaded to individual devices (our long term plan), although it is harder to predict if these options will be ready during the demonstration.

This demonstration presents live hands-on experience of the System on Chip (SoC) large-scale Field Programmable Analog Array (FPAA) IC [1] through a complete PC Board and high-level tool interface [2]. Figure 1a shows the demonstration requires only basic power connection to the laptop. The hardware includes an FPAA demonstration board and a Digilent USB device to enable a scope / function generator functionality.

We present a novel remote test system, enabled by configurable analog-digital ICs to create a simple interface for a wide range of experiments, whether in research or educational directions. Our remote test system utilizes a nearly identical setup to the existing large-scale Field Programmable Analog Array (FPAA) toolset; a mixed-mode configurable system with a common digital interface (e.g. USB) enables a nearly seamless transition. The system overhead requirements are straightforward, requiring simple email handling, available over almost all network systems with no additional requirements. We present using the FPAA devices and baseline tool framework, present overview examples for the remote system.

Figure 1 illustrates part of the user experience of the remote test system for this demonstration. This demonstration requires only basic resources (power plug and table), utilizing a wireless network as available. Participants can experience both sides of the remote system, one laptop running the remote system and infrastructure, and a second laptop (or more) only running the resulting tools and taking experimental data. Participants can try different circuits among many options already available for the user to use or modify.

This paper presents a floating-gate (FG)-based, field-programmable analog array (FPAA) system-on-chip (SoC) that integrates analog and digital programmable and configurable blocks with a 16-bit open-source MSP430 microprocessor (μP) and resulting interface circuitry. We show the FPAA SoC architecture, experimental results from a range of circuits compiled into this architecture, and system measurements. A compiled analog acoustic command-word classifier on the FPAA SoC requires 23 μW to experimentally recognize the word dark in a TIMIT database phrase. This paper jointly optimizes high parameter density (number of programmable elements/area/process normalized), as well as high accessibility of the computations due to its data flow handling; the SoC FPAA is 600 000 × higher density than other non-FG approaches.

This paper presents a floating gate Ion Sensitive Field Effect Transistor (ISFET) to monitor the activity of breast cancer cells. We use an ISFET to monitor the change in pH of the cell culture media and to observe the apoptosis of the breast cancer cells when treated with staurosporine. Since ISFETs suffer from inherent mismatch and drift in the threshold voltage, predominantly caused due to accumulation of ions on the surface of the gate, we have integrated a floating gate ISFET to calibrate the device. Floating gate ISFETs have been used to program the threshold voltage of the device either by hot electron injection, Fowler-Nordheim tunneling, and UV to remove charges. In this work we use hot electron injection to precisely program the device and tunneling as a global erase. This enables us to precisely record the changes in pH. These floating gate devices have been fabricated in 0.5 µm CMOS process.