On-device large language model (LLM) serving drives low-precision computing to address memory and compute limits. This paper presents L2Mersit, a scaling-free, range-adjustable exponent-encoded data format tailored for sub-8-bit LLM quantization. Building upon the Mersit framework, L2Mersit employs dual mode operation, comprising range-expanded and precision-enhanced modes that dynamically adapt to activation distributions with minimal control overhead. The proposed design eliminates on-the-fly scaling and auxiliary computations while effectively preserving range and precision, thereby achieving both superior perplexity and hardware efficiency. Experimental results demonstrate that L2Mersit achieves the highest accuracy among all 6-bit exponent-encoded formats while reducing the hardware complexity of auxiliary units for low-precision computing, resulting in a 62.7% area reduction.

This paper proposes an uncertainty quantification (UQ)-incorporated design optimization technique that integrates UQ considering the statistical characteristics of sensing margin with machine learning (ML) for the design of bitline sense amplifiers (BLSAs) in dynamic random access memory (DRAM), including offset compensation operation. The increased offset due to process variation exacerbated by device scaling degrades the reliability of DRAM read operations, making quantitative analysis of process variation essential. Conventional Monte Carlo (MC)-based UQ analysis provides high accuracy but requires extensive simulation costs. Accordingly, this study systematically defines key input and output variables for conventional BLSA and two representative offset compensation BLSA structures, introduces Sobol sequence-based quasi-Monte Carlo (QMC) sampling to improve simulation efficiency, and generalizes the Standard UQ methodology to predict statistical distributions of circuit performance parameters under process variation. Furthermore, a 3-Stage UQ algorithm that sequentially learns nominal, mean, and standard deviation values is proposed to enhance the efficiency of ML model training. HSPICE simulation results based on the TSMC 65 nm process demonstrated that the proposed 3-Stage UQ method reduced the simulation time required for ML training data generation by an average of 43% compared to the Standard UQ method and achieved excellent prediction performance even in data-limited environments. Additionally, design optimization combined with Bayesian Optimization (BO) confirmed performance improvements across all circuit structures. The methodology presented in this study enables effective process variation-aware optimization for DRAM designs requiring high reliability and yield, and is expected to contribute to next-generation memory circuit design automation.

Channel smoothing is widely adopted in wireless local area network (WLAN) systems to improve channel estimation, but the combination of channel smoothing and beamforming has been still a challenging work so far. The difficulty of this combination is due to the existence of discontinuities in the beamforming matrices across subcarriers. We first propose a receiver design for channel state information (CSI) feedback with a smooth beamforming matrix in an optimal way. This design is based on the optimization to maximize the cross-correlation between adjacent beamforming matrices at a cost of slightly increased feedback overhead. Then, a sub-optimal design is also proposed which has the same amount of feedback overhead as current WLANs. To further reduce feedback overhead with minimum loss of performance, machine learning (ML) technique is adopted in which the CSI quantization level is determined dynamically based on real-time channel frequency selectivity. The simulation through the IEEE 802.11be link-level simulator shows that the proposed schemes can achieve channel smoothing gain in the beamforming, improving the throughput significantly with reduced feedback overhead.

Since annotating pixel-level labels for semantic segmentation is laborious, leveraging synthetic data is an attractive solution. However, due to the domain gap between synthetic domain and real domain, it is challenging for a model trained with synthetic data to generalize to real data. In this paper, considering the fundamental difference between the two domains as the texture, we propose a method to adapt to the target domain's texture. First, we diversity the texture of synthetic images using a style transfer algorithm. The various textures of generated images prevent a segmentation model from overfitting to one specific (synthetic) texture. Then, we fine-tune the model with self-training to get direct supervision of the target texture. Our results achieve state-of-the-art performance and we analyze the properties of the model trained on the stylized dataset with extensive experiments.

Solid-state drive (SSD) has become one of the most dominant storage devices and is rapidly replacing conventional storage devices. The core component of SSD is NAND flash memory (NFM), where the actual data are stored. Cost pressure is the most critical factor limiting the further deployment of SSDs and past researches have focused on developing cost-effective high-density NFM. Although the cost-driven technology development increases per-chip capacity, it reduces channel-/way-level parallelisms for the given device capacity, resulting in the performance degradation. Such observation directs us to focus on a novel NFM architecture exploiting plane-level parallelism. The distinct features of this architecture are: 1) enabling a decoupled word-line (WL) selection for the mated planes and 2) segmenting each plane into subplanes for further maximizing the plane-level parallelism. The experimental results show that decoupled WL selection improves the throughput by up to 21.3% with a marginal overhead of less than 1%, compared to the conventional NFM architecture. In addition, adopting the plane segmentation improves the throughput by up to 43.9% with an additional overhead of 14%. Considering the tradeoff between performance and overhead, the proposed NFM architecture is a cost-efficient method to secure high performance under decreasing channel-/way-level parallelisms in high-density NFM.

The post-layout gate-level simulation constitutes a critical design step for timing closure. The major drawback of traditional post-layout gate-level simulation is its long analysis time, which becomes exacerbated as design complexity increases. An alternative method isstatictiminganalysis(STA), which can drastically reduce analysis time. However, STA sacrifices accuracy for speed and often produces unrealistic results such as false paths and overly pessimistic estimates. In this paper, we propose a hybrid analysis method that can significantly reduce analysis time, while preserving accuracy, with respect to the traditional gate-level simulation. Our key idea is that a large speedup would be possible by removing those events that are repetitious and unnecessary for simulation. In particular, we focus on reducing the number of clock-related events, which account for a major portion of all the events handled by a simulator. We tested the proposed method extensively with various benchmark circuits as well as industrial designs. Our experimental results exhibit that the proposed approach accelerates the total simulation speed by two times on average, yet maintaining the accuracy acquired by the traditional gate-level simulation.