Technology mapping involves mapping logical circuits to a library of standard cells. Traditionally, a full technology library is used, leading to a large search space and potential runtime overhead. Motivated by randomly sampled technology mapping case studies, we propose MapTune to address this challenge by utilizing reinforcement learning to make design-specific cell selection choices. By learning from the environment and guided by the reward, MapTune refines the cell selection process, resulting in a reduced search space and potentially improved mapping quality. The effectiveness of MapTune is evaluated on a wide range of benchmarks, different technology libraries, and various technology mappers. The empirical results demonstrate that MapTune achieves higher mapping accuracy and reduces delay/area across various circuit designs, technology libraries, and mappers. The article also discusses the Pareto-Optimal exploration and confirms the perpetual delay-area tradeoff. Conducted on benchmark suites ISCAS 85/89, ITC/ISCAS 99, VTR8.0, and EPFL benchmarks, the post-technology mapping and post-sizing quality-of-results (QoR) have been significantly improved, with average Area-Delay Product (ADP) improvement of 16.56% among all different exploration settings in MapTune. The improvements consistently remained for four different technologies (7 nm, 45 nm, 130 nm, and 180 nm) with various mappers including both state-of-the-art open-source and commercial synthesis tools.

Approximate computing (AC) aims to achieve energy-efficiency in digital systems by sacrificing the computational accuracy of an application. Memory-intensive applications, in which a large amount of data is processed to reach a meaningful conclusion, are the primary target. Systems for such applications consists of a large pool of compute-unit and sizeable on-chip memory. The total energy consumption for such applications is often dominated by the on-chip memory. We, therefore, focus on improving the energy efficiency of the on-chip memory by appropriately scaling down its supply voltage.

In FDSOI, sophisticated body biasing schemes can greatly reduce leakage or improve performance as well as efficiency. This paper proposes algorithms to determine body bias domain candidates which then merge those to reach a desired number of domains. Domain candidates are determined using an activation based approach, analyzing mapped verilog netlists to identify which parts of the design are used under specified conditions. Body bias domain partitionings are then determined based on activation and the timing of the partitioned parts. The algorithms include a body bias assignment algorithm to reach given timing goals with multiple domains and cross-domain resource sharing. The approach is compatible with any synthesis optimization and is resource sharing aware. Using an implementation of the proposed algorithms, overall leakage can be significantly reduced in all scenarios while obtaining the same benefits of body biasing. The method is evaluated in STMicro's 28nm FDSOI and Renesas's 65nm SOTB.

This paper introduces an FPGA-based fault injection system. To realize this system a library was developed, which implements a static mapping between a circuit described at RTL or gate-level and its corresponding placed and routed FPGA design. The aim of this mapping is to preserve module and port structure of the placed and routed FPGA design to the RT/gate-level circuit description. To demonstrate the accuracy of this mapping the ISCAS'89 benchmark circuits and the VHDL netlist of the LEON3 system are used. The results show that about 99% of the ports in the RT/gate-level circuit description can be located in the placed and routed FPGA design. Based on this library a fault injection tool was developed to accelerate the fault injection experiment time by bypassing some stages (synthesis, placement and routing) of a re-compilation process. In these experiments a 12 × speedup was achieved when compared to fault injections based on serial fault emulation.

In this work, we intend to demonstrate a number of reliability techniques developed for Coarse Grained Reconfigurable Architectures (CGRA). The techniques to be demonstrated target different portions of a System on Chip (SoC) Design consisting of a general purpose CPU, various accelerators and a CGRA which may be used for application acceleration as well. On the CGRA we will demonstrate a light-weight Triple Modular Redundancy (TMR) technique which mitigates the hardware overhead usually incurred by TMR. In case of a detected CGRA fault, we use Dynamic Remapping of the application to avoid faulty components and thus restore the functionality of the mapped application. On SoC level, we demonstrate Dynamic Functional Verification to sample and thus detect faults in components of the SoC in a time multiplexed manner. The complete system is emulated on a Field Programmable Gate Array (FPGA) for which we developed a fast and accurate fault injection method to test the developed techniques in a live and realistic way.