This article introduces an innovative approach to realize a mixer-first receiver architecture, which comprises an N-path differential architecture realized through a passive-switching network, followed by a novel self-biased active inductor-based filter. This combination allows the circuit to achieve high pass-band to stop-band attenuation and the capability to adjust and achieve the desired bandwidth and occupy less area on-chip while maintaining a high selectivity level and rejecting unwanted signals. A noise-cancelling amplifier is placed between the N-path and active inductor-based low-pass elliptic filter to reduce the noise figure of the receiver. In addition to the filter, a novel self-biased baseband amplifier with a wide bandwidth is realized, followed by a buffer to derive a 50 ohms load. The LO signal generation for the proposed receiver is obtained by implementing a passive balun circuit that operates over a wideband followed by an on-chip polyphase filter and buffer. The proof of concept is validated by implementing a designed receiver with an N-path differential architecture followed by a novel active inductor-based low-pass third-order elliptic filter, which occupies less area and achieves high selectivity compared to a passive inductor based filter on 180-nm CMOS technology. The receiver operates within the frequency range of 16-20 GHz and achieves an instantaneous single sideband (SSB) bandwidth of 160 MHz. The proposed filter achieves a pass-band to stop-band attenuation of 47 dB with a Q of 140. Additionally, the receiver exhibits an in-band compression point at -5 dBm and in-band IIP3 of 4–6 dBm with out-of-band signal linearity greater than 10 dBm.

This article presents a novel fully differential four-path passive mixer first receiver architecture, offering a wide radio frequency (RF) bandwidth and improved out-of-band (OOB) rejection. The design utilizes a current reuse approach in the process voltage temperature (PVT) resistant complementary transimpedance amplifier (TIA) to achieve excellent noise performance while minimizing power consumption. Besides, the integration of a second-order Twin-T Elliptic Low-pass Notch filter (TTE-LPNF) followed by the TIA enhances the linearity performance of the receiver and helps achieve wideband response due to positive capacitive feedback and shunting notch. The active RC-based buffer circuit is designed to efficiently drive a 50$\Omega$load impedance while providing substantial bandwidth. Moreover, the paper proposed a novel clock generator architecture based on a passive polyphase filter (PPF) and digital combinational logic that has reduced the required input local oscillator (LO) frequency by half compared to the conventional architecture for the same LO output, therefore, reducing the clock power. As a proof of concept, the proposed receiver is fabricated in TSMC 180 nm CMOS technology, and measurement is performed in the lab at room temperature. The receiver demonstrates an impressive RF bandwidth of 200 MHz while operating smoothly within the frequency range of 0.5 -2.5 GHz. The proposed mixer first receiver has achieved a conversion gain of 29 dB, a noise figure (NF) of 5.8 dB at the LO frequency of 1 GHz, and an out-of-band third-order intercept point (OOB-IIP3) of$+$18.5 dBm with power dissipation of 27 mW in signal path and 34 mW in clock path while operating at 1.8 V.

Optimizing the N-path receiver for wide input range tunability and achieving good noise, gain, and linearity performance at lower power dissipation is a challenging task. This paper investigates the negative feedback-assisted wideband reactance cancelling front-end LNA topology in the N-path direct conversion receiver in terms of its performance parameters. The proposed low-power design is enabled due to LNA preceded by the N-path mixer and has good noise performance compared to the mixer first architecture for the same signal bandwidth. The proposed reactance cancelling LNA with negative feedback has reduced the overall noise figure (NF) by the square of the feedback factor. The proposed N-path receiver designed in a 65-nm CMOS process achieves 72 - 63 dB of gain and 2.39 - 2.78 dB of NF at a minimal power dissipation of 10.69 mW. It achieved an -10 dB of S11 bandwidth for the wide input frequency range from 1–7 GHz.

An mm-wave sub-harmonic mixer using double- balanced Gilbert-cell topology in a stacked configuration is presented. The circuit applies source degenerate configuration for LO(local oscillator) input and RF (radio frequency) input in order to attain high linearity. The proposed mixer uses a switch transconductance(Sw-Gm) configuration to reduce noise Figure (NF) and obtain frequency doubling. It also helps in achieving high isolation between 2LO-to-RF (local oscillator input to radio frequency input). The proposed mixer attains more than 6 dB of conversion gain, IIP3 (third-order intercept point) of 7.94 dBm, and less than −14 dB of S11 for 40 GHz RF frequency with isolation between 2LO-to-RF of 120 dB.

A 2.4GHz novel RF Mixer with folded structure designed in 180nm RF-Mixed signal technology has been investigated. It is implemented by using double balanced transconductance switch (GmSw) configuration. The proposed mixer converts incoming signal to small signal RF current followed by PMOS current mirror structure. The circuit is designed and optimized such that it can operate at less than 1.8V of power supply. This paper proposes a design which focuses on the isolation between mixer ports. The high isolation achieved by incorporating folded structure with CMOS LO stage. In addition to that, the Mixer Common Mode Rejection Ratio (MCMRR) for the proposed folded mixer is defined in this paper. The post layout simulation has achieved 5 dB of conversion gain and 9 dBm third order input intermodulation product (IIP3). The highest isolation between LO-IF, RF-IF and LO-RF observed were up to 69 dB, 55 dB and 86 dB respectively.