Chronic pain (CP) both significantly affects individuals’ wellbeing, and complicates care for many. CP’s unpredictable nature, diverse causes, and frequent need for inter-medical-disciplinary coordination has made it a priority for bespoke digital interventions from virtual reality headsets to online fora. Many however report limited benefits from existing digital tools, and the potential of technology to enhance daily life for those with CP remains largely untapped. This paper in response embraces a participatory design approach to everyday mundane chronic pain technology. We report findings from an analysis of the r/chronicpain subreddit, focus groups conducted with the support of a national chronic pain organisation and a workshop conducted with members of this community, yielding a novel prototype pacing application. Through this paper, we contribute insight into the experience of living with chronic pain and implications for technology design and research practices to support everyday care.

Adjusting video playback speed during extensive viewing is crucial for English-as-a-Second-Language (ESL) learners to enhance their learning experience. Since existing research suggests that abrupt speed changes might negatively impact the viewing experience, several novel speed-adjustment systems have been proposed to provide adaptive and optimal video playback speed for learners. However, empirical evidence is still sparse on whether gradual adjustments truly offer a superior experience compared to immediate changes. To delve into this, we conducted a study with 32 ESL participants, comparing direct and gradual adjustments on flow state, cognitive load, and behavioral measures. Employing both objective metrics, such as pupil diameter, and subjective feedback from surveys, our results strongly favor the gradual method. It not only enhanced flow state and video comprehension but was also less obtrusive to learners. These findings underscore the advantages of gradual speed adjustment for ESL learners, offering insights for the design of next-generation speed-adjustment systems.

In this paper, we introduce an integrated power methodology for multi-core SoC designs. It features not only a bottom-up IP-based power modeling for all kinds of IP components ranging from hardware accelerators, processors, and memory blocks, but also a top-down system-wide ESL power estimation formulation. By linking these two methods of different levels of abstraction, one can thereby easily profile the power consumption of a multi-core SoC running a complete application while retaining high accuracy of estimation. We have realized the proposed methodology into two software tools: (1) PowerMixerIP, an IP-based power model builder that uses different strategies to build versatile power models for general IPs and processor IPs, and (2) PowerDepot, an ESL power estimation tool that can interact with the users in a simple way and then generate the needed power monitors to be embedded into the ESL design in SystemC for super-fast power estimation so as to facilitate early-stage system-wide power profiling. The application of these tools on a dual-core real-life designs executing an H. 264 shows that the average error of the ESL power estimation is less than 2%, while the speedup can be up to 2400X when comparing to gate-level simulation.