This article presents a path-selecting true-time delay (TTD) circuit for wideband large-scale antenna arrays. An in-depth system-level analysis of wideband arrays is conducted to demonstrate the advantage of hybrid array system steered by both phase shifters and TTDs. The corresponding TTD design requirements are derived to enable proper operation of such arrays. The proposed T-coil peaking amplifiers are incorporated to compensate for the steep frequency-scaling losses introduced by the large number of delay lines, thereby ensuring a flat gain across an ultra-wide bandwidth. A detailed design methodology for the T-coil network is presented, and multi-coil coupled floorplan are utilized to facilitate compact layout implementation. In the high-delay path, field-reinforced floorplan are adopted for artificial transmission lines to enhance area efficiency, while in the low-delay path, distributed loss-shaping networks are introduced to mitigate loss variations across different delay states. The proposed TTD circuit is fabricated in 65-nm bulk CMOS, occupying a compact chip area of 1.6$\mathrm {\times }$1.2 mm2. It achieves a measured delay range of half a nanosecond with 6-bit resolution across 6–33 GHz. The losses from delay lines are effectively compensated, yielding in an overall gain of 0 dB. The combination of wide bandwidth, large delay range, and low loss makes the proposed TTD circuit well-suited for wideband applications.

Abstract Driven by the vision of ubiquitous connectivity and wireless intelligence, the evolution of ultra-dense constellation-based satellite-integrated Internet is underway, now taking preliminary shape. Nevertheless, the entrenched institutional silos and limited, nonrenewable heterogeneous network resources leave current satellite systems struggling to accommodate the escalating demands of next-generation intelligent applications. In this context, the distributed satellite information networks (DSIN), exemplified by the cohesive clustered satellites (CCS) system, have emerged as an innovative architecture, bridging information gaps across diverse satellite systems, such as communication, navigation, and remote sensing, and establishing a unified, open information network paradigm to support resilient space information services. This survey first provides a profound discussion about innovative network architectures of DSIN, encompassing distributed regenerative satellite network architecture, distributed satellite computing network architecture, and reconfigurable satellite formation flying, to enable flexible and scalable communication, computing and control, fundamentally enhancing network resilience. The DSIN faces challenges from network heterogeneity, unpredictable channel dynamics, sparse resources, and decentralized collaboration frameworks. To address these issues, a series of enabling technologies is identified, including channel modeling and estimation, cloud-native distributed MIMO cooperation, new waveform design, grant-free massive access, nonorthogonal multicast, distributed phased array antennas, high-speed inter-satellite communication, network routing, and the proper combination of all these diversity techniques. Furthermore, to heighten the overall resource efficiency, the cross-layer optimization techniques are further developed to meet upper-layer deterministic, adaptive and secure information services requirements. In addition, emerging research directions and new opportunities are highlighted on the way to achieving the DSIN vision.

This paper presents 256-element transmitter (TX) and receiver (RX) phased arrays for satellite fixed communication at the Q and V bands, which integrate the phased-array antennas with eight-channel beamforming ICs. Wideband vector-modulated phase shifters (VGPS) and combinations of variable gain amplifier (VGA) and attenuators (ATT) are applied in the TX/RX beamforming ICs to achieve phase and gain tunings with large range and high precision. Based on the proposed beamforming ICs, the TX/RX phased arrays are realized with stacked aperture-coupled microstrip antennas on a cost-effective multi-layer PCB. Each array contains 32 TX/RX beamforming ICs, 256 antennas, and a 1-to-32 Wilkinson power divider/combiner networks. Fabricated in 65-nm CMOS technology, the packaged TX IC achieves an RMS gain error of 0.58 dB and an RMS phase error of 4.5° with 78.5-mW dc power per channel, while the$\text {OP}_{\text {1dB}}$is 9.6 dBm at 50.5 GHz. The packaged RX IC realizes a 5.3-dB NF, 0.47-dB RMS gain error, and 1.7° RMS phase error with 24.2-mW dc power per channel. The Q/V-band phased arrays are capable of scanning ±60°, while the 256-element TX phased array achieves an EIRP of 63.5 dBm. Modulated signal measurements with 200- and 400-MHz QPSK, 16-QAM and 64-QAM are also provided.

This paper presents the analysis and design of an oscillator-doubler architecture which is used to generate THz signals. In this architecture, the doubler obtains the optimum fundamental-frequency load impedance for second harmonic generation without causing problems related to instability. The oscillator creates voltages close to the optimum voltage condition, which leads to maximum power being delivered to the doubler connected to the oscillator tank. Compared to a signal generator composed of an oscillator and a conventional doubler with short-circuit load at the fundamental frequency, the proposed circuit has higher output power and DC-to-THz conversion efficiency. Based on this architecture, a 0.3-THz signal generator is designed in 40-nm CMOS. In this 0.3-THz signal generator, an inductor-sharing configuration is proposed to increase the transistor size in the cross-coupled oscillator, thus increasing the power density of the signal generator. Besides, the impact of the doubler fundamental-frequency load impedance on the conversion gain of the doubler is introduced. Also, a method of suppressing the unwanted mode in the cross-coupled oscillator is proposed. The output of this circuit is radiated through on-chip antennas. The measured radiated power and the DC-to-THz efficiency of the chip are -3.8 dBm and 0.37%, respectively, with an output frequency tuning range of 4.8%.

In this paper, the dual common-mode (CM) resonance technique is proposed for lowering the phase noise (PN) and flicker PN corner of LC voltage-controlled oscillators (VCOs) across wide tuning range. The dual CM resonator can provide high and resistive input impedance across a wide$2^{\mathbf {nd}}$harmonic band without dedicated tuning. It can both prevent the tank-loading effect and reshape the output waveform. Novel implementation methods are demonstrated to realize dual CM resonance at high frequencies. For comparison, both the dual CM resonance VCO and a reference one with a tail filter are fabricated in 65-nm CMOS, achieving the measured frequency range of 8-11.15 and 7.98-11.3 GHz, respectively. In 1/f2region, the proposed VCO shows an average PN of −139 dBc/Hz and the FOM of 190-192.3 dBc/Hz across the band, leading to an excellent FOM$_{\mathbf {T}}$of larger than 200.3 dBc/Hz. The reference VCO shows the average PN and FOM of -137.7 and 190.5 dBc/Hz. In 1/f3region, the former exhibits a low flicker PN corner of 280–350 kHz while the latter’s flicker PN corner varies largely from 290 to 950 kHz across the band. Both VCOs’ cores consume about 5 mW at 1 V supply and occupy approximately 0.13 mm2.

This paper presents a passive vector-modulated phase shifter (VMPS). The passive X-type attenuator consisting of digitally controlled transistor-array units is employed to perform the phase-invertible gain tuning, and thus enables phase shift in all four quadrants. The Wilkinson-like power combiner is utilized to sum up the quadrature signals and avoid impedance mismatches. Analysis proves that the proposed passive VMPS can provide consistent phase-shift performance for bidirectional operation. The proof-of-concept VMPS is implemented in 40-nm CMOS technology and occupies a core chip area of 0.15 mm2. Measured results prove that it can provide consistent bidirectional 6-bit phase-shift operation, with accurate phase tuning (i.e., RMS phase error <; 24°) and low gain error (i.e., ±0.6 dB) over the whole 70-90 GHz band.

Large-scale millimeter-wave (mm-Wave) integrated phased array is the key technology to enable broadband 5G and satellite communications. This paper details the design considerations, challenges and trade-offs of mm-Wave integrated phased arrays based on bulk CMOS and multi-layer hybrid PCB technologies. Both technologies attain high yield and low cost for mass production. Important beamforming building blocks are addressed and compared in detail. Demonstrators of integrated phased arrays are presented from circuit to board levels. The 1024- and 4096-element integrated phased arrays achieve the EIRP of 72.5 and 84.0 dBm respectively. Finally, relevant phased-array transceivers and antennas from the recent literature are discussed.

This article presents a Ku-band power amplifier with a series-shunt LC notch filter in 65-nm CMOS. The notch filter is integrated into the inter-stage matching network to attenuate the receiver-band noise, thereby reducing transmitter-to-receiver interference. A comprehensive analysis of the series and the shunt notch filters, as well as the position to apply the notch filter is discussed. Besides, a systematic method of optimizing passive devices in the notch filter is proposed to further improve network Q and minimize the influence on the power amplifier. Fabricated in 65-nm CMOS technology, the power amplifier prototype delivers a measured gain of 21.9 dB with 3-dB bandwidth from 13.7 GHz to 16.7 GHz at the nominal state. At 14.2 GHz, it can offer a saturated output power of 14.5 dBm with peak power added efficiency of 24.1%. The notch frequency is adjustable from 10.3 to 11.9 GHz to offer the best attenuation at the receiver band. From 10 to 12 GHz, a maximal attenuation of 30 dB is achieved. The design occupies a core area of 0.35×0.85 mm2.

In this article, a high-throughput, high-accuracy, area-efficient, and energy-efficient digital outphasing modulator (OPM) is proposed for millimeter-wave transmitters. This digital OPM is entirely based on the fixed-point unrolled and pipelined radix-2 COordinate Rotation Digital Computer (CORDIC) algorithm, which is suitable for outphasing transmitters based on both IQ and phase modulation architectures. The outphasing angle is calculated by a mixture of single-CORDIC and double-CORDIC algorithm, which significantly reduces the critical path delay. Due to architectural advantages, its error performance, sampling rate, power efficiency, and area efficiency are improved. According to FPGA implementation measurements, this architecture enables a 12-bit OPM to achieve error vector magnitude (EVM) of 0.062% and peak sampling rate of 0.74 GSample/s. According to the postlayout spice-level simulation in 65-nm CMOS, a high-throughput version can work at a peak data rate of 1.85 GSample/s at 1-V supply. A low-power version reduces the area consumption to only 0.088 mm2, consuming 28.1 pJ/Sample at 0.78 GSample/s at 0.8-V supply. The proposed high-throughput OPM with the minimized area is expected to further open up an application area of energy-efficient low-cost millimeter-wave transmitters.

In this paper, system considerations and circuit implementations for 5G millimeter-wave (mm-Wave) phased-array transceiver are presented. High data-rate and medium-range communications pose challenges for the design of phased-array transceiver circuits operating at the mm-Wave band. A possible solution is that the core chip for digital, mixed-signal and RF processing blocks are integrated in advanced CMOS, while power amplifier (PA), low-noise amplifier (LNA) and RF switch are implemented in III-V technologies (i.e., GaAs or GaN). To show the feasibility of such system architecture, key building blocks include high power amplifier (HPA), broadband LNA, amplitude-invariant phase shifter and phase-invariant variable gain amplifier (VGA) are reviewed. The proposed techniques make the mm-Wave phased-array transceiver systems suitable for 5G fixed wireless access (FWA) applications.

This paper describes a high‐speed CORDIC‐based digital outphasing modulator. Fixed‐point Matlab model of the outphasing modulator is developed to evaluate the system performance and define the circuit design parameters. Design issues such as signal quantization error, delay mismatch, and phase overflowing are addressed to enable hardware implementation. The complete outphasing modulator is fully custom designed in 40 nm CMOS, which can be integrated in a millimeter‐wave outphasing transmitter to enhance the system average efficiency. Tested with 10.56 Gb/s 64‐QAM, this work achieves an EVM of 3.2% and fulfils the IEEE 802.11ad spectral mask requirements.

This paper describes a fully integrated power amplifier (PA) in 100 nm InGaAs pHEMT process for E‐band point‐to‐point communications. The device size and biasing conditions are optimized to enhance the overall performance at millimeter‐wave frequencies. The complete PA consists of two unit PAs and each unit PA has four stages to improve the gain while ensuring stability from dc to the operating frequencies. A 4‐way zero‐degree combiner (in the unit PA) and a 2‐way λ/2 combiner are used to boost the output power. Occupying 5 mm2, the proposed PA achieves an output power of 0.45 W with 17.9% PAE at 74 GHz.

The design and optimization (both sizing and layout) of mm-wave integrated circuits (ICs) have attracted much attention due to the growing demand in industry. However, available manual design and synthesis methods suffer from a high dependence on design experience, being inefficient or not general enough. To address this problem, a new method, called general mm-wave IC synthesis based on Gaussian process model assisted differential evolution (GASPAD), is proposed in this paper. A medium-scale computationally expensive constrained optimization problem must be solved for the targeted mm-wave IC design problem. Besides the basic techniques of using a global optimization algorithm to obtain highly optimized design solutions and using surrogate models to obtain a high efficiency, a surrogate model-aware search mechanism (SMAS) for tackling the several tens of design variables (medium scale) and a method to appropriately integrate constraint handling techniques into SMAS for tackling the multiple (high-) performance specifications are proposed. Experiments on two 60 GHz power amplifiers in a 65 nm CMOS technology and two mathematical benchmark problems are carried out. Comparisons with the state-of-art provide evidence of the important advantages of GASPAD in terms of solution quality and efficiency.

Existing radio frequency (RF) integrated circuit (IC) design automation methods focus on the synthesis of circuits at a few GHz, typically less than 10 GHz. That framework is difficult to apply to RF IC synthesis at mm-wave frequencies (e.g., 60-100 GHz). In this paper, a new method, called efficient machine learning-based differential evolution, is presented for mm-wave frequency linear RF amplifier synthesis. By using electromagnetic (EM) simulations to evaluate the key passive components, the evaluation of circuit performances is accurate and solves the limitations of parasitic-included equivalent circuit models and predefined layout templates used in the existing synthesis framework. A decomposition method separates the design variables that require expensive EM simulations and the variables that only need cheap circuit simulations. Hence, a low- dimensional expensive optimization problem is generated. By the newly proposed core algorithm integrating adaptive population generation, naive Bayes classification, Gaussian process and differential evolution, the generated low-dimensional expensive optimization problem can be solved efficiently (by the online surrogate model), and global search (by evolutionary computation) can be achieved. A 100 GHz three-stage differential amplifier is synthesized in a 90 nm CMOS technology. The power gain reaches 10 dB with more than 20 GHz bandwidth. The synthesis costs only 25 h, having a comparable result and a nine times speed enhancement compared with directly using the EM simulator and global optimization algorithms.

State-of-the-art synthesis methods for microwave passive components suffer from the following drawbacks. They either have good efficiency but highly depend on the accuracy of the equivalent circuit models, which may fail the synthesis when the frequency is high, or they fully depend on electromagnetic (EM) simulations, with a high solution quality but are too time consuming. To address the problem of combining high solution quality and good efficiency, a new method, called memetic machine learning-based differential evolution (MMLDE), is presented. The key idea of MMLDE is the proposed online surrogate model-based memetic evolutionary optimization mechanism, whose training data are generated adaptively in the optimization process. In particular, by using the differential evolution algorithm as the optimization kernel and EM simulation as the performance evaluation method, high-quality solutions can be obtained. By using Gaussian process and artificial neural network in the proposed search mechanism, surrogate models are constructed online to predict the performances, saving a lot of expensive EM simulations. Compared with available methods with the best solution quality, MMLDE can obtain comparable results, and has approximately a tenfold improvement in computational efficiency, which makes the computational time for optimized component synthesis acceptable. Moreover, unlike many available methods, MMLDE does not need any equivalent circuit models or any coarse-mesh EM models. Experiments of 60 GHz syntheses and comparisons with the state-of-art methods provide evidence of the important advantages of MMLDE.