Switched-capacitor converters, commonly used for DC-DC conversion, are increasingly relevant as AC-AC signal amplifiers. This paper analyzes the AC amplifier performance metrics of the Dickson, Serial-Parallel, Fibonacci, Doubler, and Exponential charge pump topologies using small-signal, large-signal, and noise analysis. Recently published output capacitance formula are reviewed and extended, and corrected noise calculations are provided to address key errors in prior literature. Ideal and non-ideal simulation results validate the theoretical analysis and demonstrate how topology selection impacts amplifier gain, bandwidth, and noise performance in AC-AC applications. The non-ideal simulations further reveal practical limitations associated with each topology. These findings offer valuable new insights for using switched-capacitor converters as AC signal amplifiers.

In this brief, we present a fractional-N multiplying delay locked loop (MDLL) which uses a reference triggered ring oscillator (RTRO) as a coarse digital-to-time converter (DTC) to reduce a required fine DTC range by 1/10, improving its linearity. The RTRO’s period is a programmed offset from the MDLL period so that each RTRO cycle effectively adds a delay to the reference clock. As a result, the fine DTC range only needs to cover the programmable coarse step, allowing > 9x range reduction, relaxing the design requirements of the DTC. The RTRO and MDLL periods are regulated by frequency locked loops (FLLs) that use a bang-bang phase detector (BBPD) to detect errors. Delay Locked Loops (DLLs) are used to regulate the DTC delays and absorb the offsets introduced by each BBPD. An LMS algorithm-based background calibration is used for correcting the fine DTC gain. To prove the concept, we designed the MDLL in a 65nm CMOS process. Verilog simulation with block-level models based on parasitic-layout transistor-level simulation results are used to evaluate the performance. A RMS jitter of 141.3fs was achieved at 3.00005GHz with a 50MHz reference clock, achieving a -246.7 dB FoM. The worst case fractional spur and reference spur are -69.2 dBc and -55.5 dBc, respectively.

This work presents an output-capacitor-free synthesizable LDO with a novel hybrid controller architecture to overcome poor PSRR problem of Digital LDOs (DLDOs) at low frequencies. The architecture employs a synthesizable PID controller as the digital controller and uses a low-bandwidth amplifier to modulate the drive strength of the digital current switches in steady state. The hybrid LDO is fabricated in a 65nm process and occupies an area of 0.09164mm2. The LDO has an output current range of 1mA - 82mA at 50mV dropout, a PSRR or -12.25dB @1kHz and achieves a 3.32ps fast response time with 99.87% peak current efficiency resulting in a FOM of 4.3fs.

This work presents a fully integrated 28nm wake-up radio (WRX) for the NB-IoT protocol that includes a novel low-power OFDM digital baseband wake-up detector in addition to a low-noise RF front-end. This co-optimized WRX achieves the highest degree of integration for an NB-IoT WRX and is the only NB-IoT WRX to receive and process protocol standard OFDM signals on-chip. The digital baseband utilizes a 12-point FFT engine optimized for the NB-IoT Wake Up Signal (WUS), which reduces power consumption compared to a radix-2 implementation. This fully integrated WRX occupies an area of 2mm2and can be used stand-alone to wake up a main NB-IoT radio without the need to utilize an external digital modem or ADC. This WRX greatly reduces the power consumption of duty-cycled NB-IoT systems, increasing battery life without increasing latency.

This paper presents an integrated ultra-low power (ULP) analog front-end (AFE) for motion sensing applications with off-the-shelf passive infrared (PIR) sensors. Existing PIR-sensor-based motion sensing systems suffer from high power consumption due to the large power overhead of the sensor as well as the analog processing circuitry. In this work, a novel discrete-time signal processing approach is proposed to enable aggressive duty cycling of the PIR sensor, reducing the sensor’s average power by 1944x (from 175µW to 90nW). The AFE is fabricated in 180nm CMOS and consumes 1.41µW. This work is the first integrated ULP motion sensing front-end for PIR sensors.

This work presents a methodology to automate the design and layout implementation of a low dropout (LDO) regulator from the user specified performance requirements. The proposed methodology adopts LDO architectures compatible with cell-based design process, as the template architectures to achieve the synthesis of LDO analog specifications. An auxiliary-cell (auxcell) library with mixed signal components compatible with standard-cell grid placement, is implemented to enable the cell-based design automation. The automation process includes a technology-agnostic modeling step to determine the performance of auxcells and the overall LDO design, making this methodology highly robust. A python based LDO generator tool using the proposed methodology is implemented to demonstrate LDO designs in 130nm, 65nm and 12nm CMOS processes. Similar to that of digital standard cell libraries, there is a one-time cost of auxcell library preparation when porting the LDO generator to a new technology node. A commercial place-and-route tool is then used to implement the layout of both the digital and mixed-signal blocks, outputting final GDS with no additional custom layout required. The generator has a baseline design with I-controller, for synthesis of DC input specifications (input voltage, dropout, ripple, output load and output cap). Synthesis of transient input (max undershoot/overshoot, min load step time) specifications is achieved by integrating synthesizable P/PD control loops with the baseline. LDO designs with fast transient response, minimum load transition times of 2ns and FOMs >59.2fs, have been implemented and verified with post-PEX simulations using this generator.

This work presents an open-source methodology to automate the design and layout of a low dropout (LDO) regulator from high-level performance specifications. LDO designs with this methodology have been demonstrated in commercial 65nm, 12nm, 130nm processes and the open-source 130nm Skywater PDK. The tool currently supports LDO designs with 50mV/100mV dropout for an input voltage range of 0.6V-1.3V (130nm and 65nm), 0.6V-0.9V (12nm), 1.8V-3.3V (Skywater 130nm) and a maximum load current ranging from 0.5mA-25mA (130nm and 65nm), 1mA-20mA (12nm), 0.5mA-50mA (Skywater 130nm). Cell-based design approach is adopted using an auxiliary cell library to enable mixed-signal design synthesis. A port to a new technology only requires a one-time manual layout for auxiliary library generation. The design automation includes a technology-agnostic modeling step and generates the LDO layout automatically. A bi-directional shift register based DLDO with a 1-bit comparator and a stochastic flash ADC (achieving 15x faster settling time) for error detection has been generated using the tool and validated using silicon measurements from 65nm process. LDO designs with different switch types and load configurations have been fabricated in open-source Skywater 130nm.

This article presents modeling and design optimization of switched-capacitor charge pumps for use as cold-start circuits in photovoltaic energy harvesters. For a successful cold-start from photovoltaic energy, a certain output voltage and current must be generated by the charge pump while jointly minimizing the required input voltage and current from the energy harvesting source. We model the operation of the cold-start charge pump including its oscillator, derive expressions for required input voltage and current based on output requirements, and demonstrate a Pareto-optimal design space that defines the tradeoff between the required input voltage and current to achieve cold-start. We then assess the impacts of process and temperature variation, and suggest a general design methodology for cold-start charge pump circuits. Finally, we validate models with measurements from a design fabricated in 55nm CMOS.

This paper presents an ultra-low power (ULP) node-controlling system-on-chip (SoC) used for power-mode management and phantom energy reduction of miscellaneous electric loads (MELs). The SoC is powered from a single 2.5 V voltage supply enabled by the integrated power management unit (PMU) and can control up to 16 MELs due to the on-chip 16-channel correlator and the 32b RISC-V microprocessor. To further reduce the system power consumption, two clock domains have been adopted for the correlator and the processor separately. Fabricated in 65-nm CMOS, the measured minimum power consumption of the proposed SoC is only 85 nW at 0.45 V voltage supply and 1 kHz clock frequency. The measured maximum operating frequency can go up to 148 kHz with a 0.55 V supply. An application experiment successfully demonstrates that the SoC controls the power modes of MELs from wake-up to cut-off to save the average power and phantom energy.

We present the world's first autonomous mixed-signal SoC framework, driven entirely by user constraints, along with a suite of automated generators for analog blocks. The process-agnostic framework takes high-level user intent as inputs to generate optimized and fully verified analog blocks using a cell-based design methodology. Our approach is highly scalable and silicon-proven by an SoC prototype which includes 2 PLLs, 3 LDOs, 1 SRAM, and 2 temperature sensors fully integrated with a processor in a 65nm CMOS process. The physical design of all blocks, including analog, is achieved using optimized synthesis and APR flows in commercially available tools. The framework is portable across different processes and requires no-human-in-the-Ioop, dramatically accelerating design time.

The creation of cell-based ring-oscillators using digital place-and-route tools has emerged as a practical solution to the difficulties of designing these circuits in advanced process nodes. However, design iteration and verification for these circuits today rely on complete SPICE simulations which can be slow and costly. In this paper, we present a static timing analysis approach to the design and verification of these oscillators. This approach provides up to a 20x reduction in verification time, and allows for automated refinement of oscillator designs within the digital design flows. Experimental results show agreement with SPICE simulations and illustrate simulation and design time savings.

This paper presents implementation and validation of innovative back-channel wireless communication techniques for ultra-low power (ULP) devices. Back-channel schemes allow ULP devices that are not WiFi-compliant to communicate with already-deployed WiFi infrastructure without any hardware modification. This paper introduces an improved payload bit crafting procedure to create back-channel messages embedded in standard WiFi OFDM packets. In addition, the concept of bi-directional WiFi back-channel is newly introduced and validated in the prototype system. Using a commercial WiFi chip and Universal Software Radio Peripheral (USRP) X310 hardware platform, two downlink back-channel schemes as well as an uplink back-channel scheme are successfully demonstrated rendering realistic real-time communication performance. Field trials are performed for over-the-air wireless back-channel bi-directional communications. System characterization confirms that the proposed back-channel can operate at lower signal-to-noise ratio than what standard WiFi systems require.

In this paper, we present an innovative back-channel wireless communication concept. The proposed back- channel communication enables ultra-low power (ULP) devices that are neither WiFi (IEEE 802.11a/g/n) nor Bluetooth Low Energy (BLE) compliant to receive messages from both WiFi and BLE transmitters. This allows communication between heterogeneous devices beyond the boundary of WiFi and BLE standards without hardware modification on already-deployed infrastructure. Back- channel messages are created in frequency shift keying (FSK) modulation format by feeding carefully crafted bit sequences in the payload of the WiFi or BLE packets. Systematic algorithms are introduced to embed any desired back-channel messages in FSK format on WiFi and/or BLE compliant packets. Using a commercial off-the-shelf (COTS) narrowband FSK receiver, we demonstrate successful reception of back-channel messages from WiFi and BLE transmitters. Although this COTS narrowband FSK receiver is not specifically designed for the back-channel communication, less than 1% packet error rate (PER) is achieved, validating the concept of software defined back- channel communication among heterogeneous wireless devices.

This paper presents an energy-autonomous wireless communication system for ultra-small Internet-of-Things (IoT) platforms. In the proposed system, all necessary components, including the battery, energy-harvesting solar cells, and the RF antenna, are fully integrated within a millimeter-scale form factor. Designing an energy-optimized wireless communication system for such a miniaturized platform is challenging because of unique system constraints imposed by the ultra-small system dimension. The proposed system targets orders of magnitude improvement in wireless communication energy efficiency through a comprehensive system-level analysis that jointly optimizes various system parameters, such as node dimension, modulation scheme, synchronization protocol, RF/analog/digital circuit specifications, carrier frequency, and a miniaturized 3-D antenna. We propose a new protocol and modulation schemes that are specifically designed for energy-scarce ultra-small IoT nodes. These new schemes exploit abundant signal processing resources on gateway devices to simplify design for energy-scarce ultra-small sensor nodes. The proposed dynamic link adaptation guarantees that the ultra-small IoT node always operates in the most energy efficient mode for a given operating scenario. The outcome is a truly energy-optimized wireless communication system to enable various classes of new applications, such as implanted smart-dust devices.

This paper presents innovative back-channel wireless communication techniques for ultra-low power (ULP) devices. The concept of embedded back-channel communication is proposed to enable a variety of new applications by inter-connecting heterogeneous ULP devices through existing orthogonal frequency division multiplexing (OFDM)-based WiFi (IEEE 802.11a/g/n/ac) networks. The proposed back-channel communication allows ULP devices to decode messages embedded in WiFi OFDM packets even if these ULP devices are incapable of demodulating OFDM. The proposed back-channel signaling has unique properties that are easily detectable by non-WiFi ULP receivers consuming sub-mW of active power. The proposed scheme eliminates the need for specialized transmitter hardware or dedicated channel resources for embedded back-channel signal transmission. Instead, carefully sequenced data bit streams will generate back-channel messages from already-deployed WiFi infrastructure without any hardware modification. This paper demonstrates that WiFi OFDM back-channel communication is feasible in various modulation formats, such as pulse position modulation, pulse phase shift keying, or frequency shift keying. Systematic algorithms are unveiled to create back-channel messages in various modulation formats from a WiFi standard compliant datapath. Comprehensive bit error rate performance analysis of various WiFi back-channel communication schemes is derived and validated in realistic multi-path frequency selective fading channels.

A hardware accelerator is presented to compute the probabilistic inference for a Bayesian network (BN) in distributed sensing applications. For energy efficiency, the accelerator is operated at a near-threshold voltage of 0.5 V, while achieving a maximum clock frequency of 33 MHz. Clique-tree message passing algorithm is leveraged to compute the probabilistic inference. The theoretical maximum size of a factor that the proposed hardware accelerator can handle is 2(8×20)=160 entries, which is sufficient for handling massive BNs, such as PATHFINDER, MUNIN, and so on (>1000 nodes). A Logical Alarm Reduction Mechanism (ALARM) BN is used to benchmark the performance of the accelerator. The accelerator consumes 76 nJ to execute the ALARM network using a clique-tree message-passing algorithm, while the same algorithm executed on an ultralow-power microcontroller consumes 20 mJ.

This article provides the latest advances from the NSF Advanced Self-powered Systems of Integrated sensors and Technologies (ASSIST) center. The work in the center addresses the key challenges in wearable health and environmental systems by exploring technologies that enable ultra-long battery lifetime, user comfort and wearability, robust medically validated sensor data with value added from multimodal sensing, and access to open architecture data streams. The vison of the ASSIST center is to use nanotechnology to build miniature, self-powered, wearable, and wireless sensing devices that can enable monitoring of personal health and personal environmental exposure and enable correlation of multimodal sensors. These devices can empower patients and doctors to transition from managing illness to managing wellness and create a paradigm shift in improving healthcare outcomes. This article presents the latest advances in high-efficiency nanostructured energy harvesters and storage capacitors, new sensing modalities that consume less power, low power computation, and communication strategies, and novel flexible materials that provide form, function, and comfort. These technologies span a spatial scale ranging from underlying materials at the nanoscale to body worn structures, and the challenge is to integrate them into a unified device designed to revolutionize wearable health applications.

With advances in telecommunications, an increasing number of services rely on high data rate spectrum access. These critical services include banking, telemedicine, and exchange of technical information. As a result, spectrum resources are in ever-greater demand and the radio spectrum has become overly crowded. For efficient usage of spectrum, smart or cognitive radios are sought after. However, current wireless phones can only select a few specific bands. In this paper, we discuss the advantages of reconfigurable radios in not only increasing the efficiency of spectrum usage but also in potentially reducing the cost of wireless handsets and the barriers for new wireless service providers to enter the market. We review available technologies that make the implementation of reconfigurable radios possible and discuss technical challenges that need to be overcome before multistandard reconfigurable radios are put into practice. We also evaluate the ability of reconfigurable radios in reducing entry costs for new competitors in wireless service.

The proximity effect of tungsten-filled through-silicon-vias (TSVs) on the threshold voltage and mobility of CMOS devices due to mismatch in thermal expansion coefficients is modeled and verified with measurements. Test structures fabricated in a two-layer 130-nm CMOS 3-D integrated circuit process are measured and compared with 3-D finite element method simulations. Results show that the threshold voltage is not affected by TSVs, whereas mobility is affected by up to 10% for devices within 4 μm of a TSV.

Body sensor networks (BSNs) are emerging cyber–physical systems that promise to improve quality of life through improved healthcare, augmented sensing and actuation for the disabled, independent living for the elderly, and reduced healthcare costs. However, the physical nature of BSNs introduces new challenges. The human body is a highly dynamic physical environment that creates constantly changing demands on sensing, actuation, and quality of service (QoS). Movement between indoor and outdoor environments and physical movements constantly change the wireless channel characteristics. These dynamic application contexts can also have a dramatic impact on data and resource prioritization. Thus, BSNs must simultaneously deal with rapid changes to both top–down application requirements and bottom–up resource availability. This is made all the more challenging by the wearable nature of BSN devices, which necessitates a vanishingly small size and, therefore, extremely limited hardware resources and power budget. Current research is being performed to develop new principles and techniques for adaptive operation in highly dynamic physical environments, using miniaturized, energy-constrained devices. This paper describes a holistic cross-layer approach that addresses all aspects of the system, from low-level hardware design to higher level communication and data fusion algorithms, to top-level applications.

Wafer testing via direct-contact probe cards has long been an effective and relatively low-cost method for testing integrated circuit (IC) chips prior to packaging. However, the physical contact occurring between the wafer and automatic test equipment (ATE) has significant costs due to contact point deformation and the need for abrasive cleaning. In this paper, we investigate a non-contact testing technique that wirelessly couples an IC wafer and ATE, and serves as an alternative to conventional probe-card testing. We derive several analytical models for a capacitive testing channel. Electromagnetic field simulations results are presented that support the proposed channel models. We conclude that capacitance-based wireless testing is feasible for testing ICs in the 1-GHz range.

Non-coherent UWB receivers are often implemented using energy detection architectures which are very sensitive to noise in the channel and interference. Therefore, the receiver bandwidth plays an important role since the total noise and interference energy is proportional to this bandwidth. This work provides analytical expressions to find the optimal receiver bandwidth and quantifying the effect on the bit-error-rate (BER) due to channel noise and adjacent-channel interference (ACI). A reduction in receiver bandwidth beyond the optimal point is shown to have minimal impact on BER performance when ACI is negligible.

This paper presents a low-power technique for harvesting a clock from the Global System for Mobile Communications (GSM) cellular network for the purpose of waking up and synchronizing nodes in a wireless sensor network. The 21-Hz clock is embedded within the broadcast channel of every GSM cell worldwide, making it a pervasive synchronization source. A low-power receiver architecture is presented to harvest the signal. Based on simulation results, the architecture can extract the clock with an error probability of less than 10-4. Finally, a discrete prototype was built to verify the functionality of the receiver architecture.

Modern Ultra-Wide Band (UWB) regulations have recently been adopted worldwide allowing for unlicensed operation within 3.1 and 10.6 GHz, using an appropriate wideband signal format with a low Effective Isotropic Radiated Power (EIRP) level. UWB characteristics are suitable to transmit data using pulses instead of continuous-waves such as in narrowband radio links. It has the potential to be the right technology for high data-rate, low-power and short-to-medium range communication systems. We will focus on Impulse Radio-UWB (IR-UWB) systems and show their suitability for many different applications, including sensor networks, ad-hoc networks, cognitive radio, home networking, etc. We will also discuss the difficulties and challenges of designing IR-UWB systems. We present a tutorial overview of UWB regulations and usable signals. We present the existing standards and recommendations, and we review recently published results, highlighting trends in UWB transceiver power consumption and the impact of CMOS scaling on performance.

This paper presents two impulse radio ultrawideband (IR-UWB) transmitters which are synthesized from standard digital library components. All functional blocks in the transmitters are implemented with digital standard cells, and placed-and-routed (PAR) by automatic design tools; therefore the transmitter is portable and scalable to other process technologies. To verify the feasibility of the architecture, the transmitter is implemented in a FPGA device, then, fabricated in a 65nm CMOS process. The 65nm CMOS transmitter occupies 0.0375mm2, and the active energy consumption while pulsing is 90pJ/pulse.

This paper presents a synthesizable cyclic Vernier time-to-digital converter (TDC) with digitally controlled oscillators (DCOs). All functional blocks in the TDC are implemented with digital standard cells and placed-and-routed (PAR) by automatic design tools; thus, the TDC is portable and scalable to other process technologies. The effect of PAR mismatch is characterized in the post-layout simulation and utilized to achieve 1ps TDC resolution. The TDC was designed in a 65nm CMOS process, and occupies 0.001mm2.

Ultra-wide-band (UWB) communication has a variety of applications ranging from wireless USB to radio frequency (RF) identification tags. For many of these applications, energy is critical due to the fact that the radios are situated on battery-operated or even batteryless devices. Two custom low-power impulse UWB systems are presented in this paper that address high- and low-data-rate applications. Both systems utilize energy-efficient architectures and circuits. The high-rate system leverages parallelism to enable the use of energy-efficient architectures and aggressive voltage scaling down to 0.4 V while maintaining a rate of 100 Mb/s. The low-rate system has an all digital transmitter architecture, 0.65 and 0.5 V radio-frequency (RF) and analog circuits in the receiver, and no RF local oscillators, allowing the chipset to power on in 2 ns for highly duty-cycled operation.

Long distance, low data-rate UWB communication for sensor network applications requires a highly energy efficient transceiver combined with circuit and system-level optimizations to maximize range. A custom pulsed-UWB transceiver chipset in 90 nm CMOS is presented that targets these aggressive specifications. The transceiver efficiently communicates at data rates from 0-to-16.7 Mbps in three 550 MHz-wide channels in the 3.1 to 5 GHz band by using pulse position modulation (PPM). The transmitter uses an all-digital architecture and calibration technique to synthesize pulses with programmable width and center frequency. The non-coherent receiver operates at 0.65 V and performs channel selection Altering, energy detection, and bit-slicing. As FCC regulations limit the maximum transmit power of UWB communication, a run-length limiting technique is presented to reduce energy requirements when maximizing range at low data rates.

This paper proposes a practical and effective modulation technique applicable to pulsed-UWB systems that mimics the desirable, continuous spectrum of a BPSK signal without requiring an inversion in the signal path. This technique can be used for scrambling the spectrum of a PPM signal, or as a replacement for BPSK signaling. It has been implemented in an all-digital, delay line based UWB transmitter in 90 nm CMOS. An analysis of the spectral characteristics of the modulation technique is given, as well as simulation and measured results.

Ultra-wideband (UWB) communication is an emerging wireless technology that promises high data rates over short distances and precise locationing. The large available bandwidth and the constraint of a maximum power spectral density drives a unique set of system challenges. This paper addresses these challenges using two UWB transceivers and a discrete prototype platform.

This tutorial paper examines architectural and circuit design techniques for a microsensor node operating at power levels low enough to enable the use of an energy harvesting source. These requirements place demands on all levels of the design. We propose architecture for achieving the required ultra-low energy operation and discuss the circuit techniques necessary to implement the system. Dedicated hardware implementations improve the efficiency for specific functionality, and modular partitioning permits fine-grained optimization and power-gating. We describe modeling and operating at the minimum energy point in the subthreshold region for digital circuits. We also examine approaches for improving the energy efficiency of analog components like the transmitter and the ADC. A microsensor node using the techniques we describe can function in an energy-harvesting scenario.