The level of confidence in a VHDL description directly depends on the quality of its verification. This quality can be evaluated by mutation-based test, but the improvement of this quality requires tremendous efforts. In this paper, we propose a new approach that both qualifies and improves the functional verification process. First, we qualify test cases thanks to the mutation testing metrics: faults are injected in the design under verification (DUV) (making DUV's mutants) to check the capacity of test cases to detect theses mutants. Then, a heuristic is used to automatically improve IPs validation data. Experimental results obtained on RTL descriptions from ITC'99 benchmark show how efficient is our approach.

In order to improve the testability of asynchronous NoCs, we have developed a design-for-test (DfT) architecture. In this architecture, each asynchronous network node is surrounded by an asynchronous test wrapper and the network communication channels are reused to establish high throughput TAMs. A special block, the generator-analyzer-controller (GAC) unit, has also been developed to generate test vectors, to control test flows, and to analyze the test results. This unit can be implemented on-chip or off-chip (in our experiments, it has been implemented off-chip). The operation of the test wrappers is controlled by a dedicated 2-bit configuration channel. Thanks to its scalability and versatility, the proposed architecture can be configured to adapt to any NoC topology and to any specific application.

The expansion of Wireless Systems-on-Chip leads to a rapid development of design and manufacturing methods In this paper, the test vectors used for design validation of AMS & RF SoCs are evaluated and optimized. This qualification is based on a fault injection method. A fault model based on variation of behavioral parameters and a related qualification metric are proposed. This approach is used in the receiver’s design of a WCDMA transceiver. A test set defined by verification engineers during the validation of this system is qualified and optimized. Then, this test set is compared with a second test set automatically generated by a developed tool.

Software simulation remains the most used method for VHDL RTL functional verification. The functional verification process essentially consists of two parts. The first one is the functional qualification; the second one is the qualification- driven stimuli generation. Currently, the qualification and the generation tasks are iterative processes based on VHDL simulation which is dramatically time consuming. The simulation time increases with the circuits’ size and the required level of quality. In our previous works, we have proposed some approaches based on the mutation testing technique to evaluate and to improve functional validation quality. Now, to reduce this simulation time, we propose in this paper a new approach based on FPGA emulation. So, an hardware-software platform called “Meta-Mutant Testbench” is used to emulate mutants. Experimental results for some ITC’99 benchmark circuits show that our mutation emulator is about 20 times faster than classical software simulators; this speedup increases with the circuits’ size.

The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these network architectures. To test the SoCs, the main challenge is to reach into the embedded cores (i.e, the IPs). In this case, the DFT techniques that integrate test architectures into the SoCs to ease the test of these SoCs are really favoured. In this paper, we present a new methodology for testing NoC architectures. A modular, generic, scalable and configurable DFT architecture is developed in order to ease the test of NoC architectures. The target of this test architecture is asynchronous NoC architectures that are implemented in GALS systems. The proposed architecture is therefore named ANoC-TEST and is implemented in QDI asynchronous circuits. In addition, this architecture can be used to test the computing resources of the networked SoCs. Some initial results and conclusions are also given.

The authors' goal is to produce validation data that can be used as an efficient (pre) test set for structural stuck-at faults. In this paper, we detail an original test-oriented mutation sampling technique used for generating such data and we present a first evaluation on these validation data with regard to a structural test.

We propose the use of accessibility measures in some testing strategies to specify testing objectives based on a functional model. The functional model, which is founded on the information transfer within software, was used with success to analyze testability for data-flow software. The testing strategies based on this model allow specification of testing objectives in relation to faults diagnostic, i.e. they allow not only faults to be detected but also to be located in the software. The approach is applied on a dataflow design provided by THALES Avionics to specify testing objectives.

In this paper, we propose to use the static single assignment form, which was originally proposed for code optimization in compilation techniques, in order to transform software components into a data-flow representation. Thus, hardware testability concepts can be used to analyze the testability of components that are described by C or Ada programs. Such a testability analysis helps designers during the specification phases of their components and testers during the testing phases to evaluate and eventually to modify the design.

This paper proposes a systematic methodology for improving functional validation vectors developed to check digital circuits. This method exploits the mutation testing concept originally proposed for software validation. Mutation injects specific functional transformations in circuit descriptions expressed in languages like VHDL or Verilog. These programs, called mutant, are syntactically correct but functionally incorrect. Knowing how these vectors detect functional faults improves the confidence in the design and provide information on the coverage of validation vectors. The paper identifies limits of previous work on mutation testing applied to hardware and proposes method that are better suited to the task.

High testability is a strongly desired feature of software, since it tends to make the validation phase more efficient in exposing faults during testing, and consequently it increases the quality of the end-product. Furthermore, testability is a criterion of crucial importance to software developers, since the sooner it can be estimated, the better the software architecture will be organized to improve subsequent maintenance. This paper is concerned with the testability of data flow software designs, its definition, and the axiomatization of its expected behavior. This behavior is expressed in relation to basic operations that are applicable on designs, and to the dedicated test strategies which are selected. Measurements are proposed which are consistent with the stated axioms. The whole approach is demonstrated using design specifications of embedded software developed in the avionics industry.

This paper is concerned with diagnosability, its definition and the axiomatization of its expected behaviour. The intuitive expected behaviour of diagnosability is defined relative to basic operations that are applicable on software designs. A diagnosability measurement is proposed which is consistent with the stated axioms. The diagnosability metric is based on an analysis of the design structure: fault location effort and precision are measured for a given testing context. Compromises between global test difficulty and diagnostic precision are illustrated on part of a data-flow software design. Throughout the paper, we develop a case study.

This paper presents a unified approach which allows efficient concurrent tests to be considered when synthesizing scalable signal processing multiprocessor architectures. The approach is based on two earlier works. The first work has allowed the synthesis of scalable multiprocessor architectures where comparison testing is considered. The second work has shown the feasibility of using a software technique called mutation testing to successfully test hardware devices. The presented approach ensures that VLSI digital signal processors (DSP) are totally tested concurrently within useful computation. Based on realistic examples of signal processing applications and state-of-the-art DSPs, the approach is shown to be highly efficient in terms of fault coverage and fault latency.

In this paper, we focus on high level design diagnosis. A novel diagnosis strategy is presented which allows faults to be automatically located. Given a system under test, this method effectively restricts the suspected parts in order to correct the detected faults.

This paper presents an off-line diagnosis strategy for parallel message-passing systems. This strategy, called host-diagnosis, allows an external observer, i.e. the host system, to perform centralized diagnosis of the system state, given results of distributed tests performed among the system processors. Three algorithms that use the host-diagnosis strategy are proposed. The performance of the three algorithms are evaluated and compared to those of a classic distributed self-diagnosis algorithm. The obtained results show an interesting behaviour of the host-diagnosis algorithms in comparison with the self-diagnosis one.

This paper proposes a new approach of VP testing and reporting functions and highlights the close co-operation that can be established between VP fault management and self-healing mechanisms in order to enhance the efficiency of the distributed recovery approaches in case of failures. The still unused fields in the operation and management flows defined for ATM networks can be reserved for self-healing requirements in order to prepare the restoration and consequently optimise ATM network protection.

With the great advancement in the design automation field, actual tools allow to describe hardware systems as software programs using high-level hardware description languages such as VHDL or VERILOG. Consequently, a design fault which affects the system specification can be considered as a software fault. To test the system specification against (software) design faults, we propose in this paper an adaptation of the mutation analysis, originally proposed for software testing, to test VHDL functional descriptions. The resulted test set is applied on the gate-level structure of the system to measure its capacity to uncover hardware faults such as the stuck-at faults. Heuristics to enhance the test set in order to be sufficient for testing hardware faults are presented and results are compared to traditional ATPGs. Accordingly, this paper presents a unified method for testing both the system specification and the hardware implementation.

In this paper a test-based hardware/software partitioning approach is presented for a co-design specification. Depending on the hardware or software implementation choice for each unit-level component, the test cost for the whole system is evaluated. The unit test costs are estimated by means of mutation-based analysis with respect to the implementation choices.

This paper deals with off-line testing of parallel systems. The applicability of distributed self-diagnosis algorithms is investigated. Both static and adaptive testing assignment strategies are studied and evaluated using a queueing network model of the system under test. Key results include testing latency and message load of each algorithm.

This paper focus on the testability analysis of co-designed data-flow specifications. The co-designed specification level implies a high level testability analysis, independent of the implementation choices. With respect to testability, the difficulties of generating test sets, detecting and diagnosing faults are discussed and estimates are proposed. A hardware modelling, based on information transfers and called the Information Transfer Graph, is adapted to the specifications. A real case study supplied by Aerospatiale illustrates all the evaluations.

The paper deals with the testability analysis of dataflow co designed systems. As a data flow specification is independent from the hardware/software implementation choice, a uniform approach may be used to evaluate the specification with respect to testability. The difficulty of generating test sets, and of detecting and diagnosing faults is discussed and estimated. We chose to use an existing hardware testability model which is suitable for data flow software specification; this model, based on information transfers, is called the Information Transfer Graph. A real case study supplied by Aerospatiale illustrates the proposed testability estimates.

A practical testing strategy is presented for locating faults occurring on both cells' routing parts and internal physical lines within a 2D massively parallel machine. We present first an approach which does not consider all practical constraints. Then, an approach based on IEEE 1149.1 standard is studied and its efficiency is illustrated. The results obtained are given.

This paper presents the application of some hardware testability concepts to data-flow software. Testability is concerned with three difficulties: generating test sets, interpreting test results and diagnosing faults. This threefold aspect of testability is discussed and estimates are proposed.

This paper studies the reconfiguration problem within a 2D MIMD machine, once the testing process is accomplished. For that, three fault-tolerant routing algorithms are proposed and their efficiency illustrated. The implementation results are also given.

An expert system prototype is presented whose aim is to select a test strategy for complex devices, logic PC boards, or systems. Given a set of resources on the board and a set of functions which are performed using these (or a subset of these) resources, the expert system produces a sequence of functions through which the board should be tested. The sequence should be among the best according to a set of criteria (testability, complexity) and subject to constraints (testability threshold, priority). The obtained sequence can be used for developing functional tests. A minimum set of rules is defined as well as default evaluation functions in order to simulate the strategy's evolution. This prototype allows verification of the method validity on various examples. The expert system, written in OPS5 language, runs on VAX. It is made up of 350 production rules, of which 250 concern the strategy tree exploration and 100 are related to the type-1 and type-3 knowledge.>

The goal of the paper is to propose test methods for wired or microprogrammed control units without special test facilities: no special access path, i.e., no direct and exhaustive observation means. Consequently, the control unit will be tested through the current control algorithms under "normal" sequencing facilities and through the controlled operative part; the proposed methodology consists of choosing an adequate set of algorithms and specific data, allowing an efficient test with respect to errors hypothesis.

Our purpose is to define a methodology for writing (micro) programs to test CPU's for which no or few test facilities are available.

Two different test methods, specific to two control mechanisms in a logic network are presented. These methods, in fact, correspond to two levels of complexity and therefore to two kinds of hardware realizations. The main considerations will be the following.