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Ying Gao 0001

dblp:15/1300-1 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · unresolved

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Software engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Cloud and datacenter computing · 50% Interconnection networks and networks-on-chip · 38% Processor architecture and microarchitecture · 12%
Network and information security
1 paper
Hardware security and side channels · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › network-on-chip design
network-on-chip security
0.212013
SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip · ISCA 2013
Cloud and datacenter computing › resource management › resource multiplexing
time-division multiplexing
0.212013
SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip · ISCA 2013
Hardware security and side channels
trusted execution environments
0.012013
SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip · ISCA 2013
Processor architecture and microarchitecture
chip multiprocessor
0.012013
SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip · ISCA 2013
Cloud and datacenter computing
performance isolation
0.012013
SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip · ISCA 2013

Methods — techniques the papers use, named apart from their topics

time-division multiplexing · 0.3
YearPublicationVenuePosition
2013 SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip
abstract
As multicore processors find increasing adoption in domains such as aerospace and medical devices where failures have the potential to be catastrophic, strong performance isolation and security become first-class design constraints. When cores are used to run separate pieces of the system, strong time and space partitioning can help provide such guarantees. However, as the number of partitions or the asymmetry in partition bandwidth allocations grows, the additional latency incurred by time multiplexing the network can significantly impact performance.
Hassan M. G. Wassel, Ying Gao 0001, Jason Oberg, Ted Huffmire, Ryan Kastner, Fred Chong, Timothy Sherwood
ISCA2