Burstable billing is widely adopted by colocation data center providers to charge their users for data transferring. This paper proposes a cost-aware traffic management approach for a colocation data center user under burstable billing where it is charged based on the 95th percentile bandwidth usage. To do this, we first develop a tractable mathematical expression to calculate the 95th percentile usage of a user. Then, we develop an optimization problem to maximize the user's surplus based on both deterministic and stochastic predictions of the user's demand. We show that the resulted optimization problem, while non-convex by nature, can be efficiently solved or approximated using a convex program. We also show that the proposed approach can also be applied in a more general scenario where the user gets services from multiple service providers. Using real-world workload traces, we show that the proposed approach can reduce a colocation data center user's IP transit cost by 26 percent and increase its total surplus by 23 percent, compared to the current practice of allocating bandwidth on-demand.

Geographical load balancing (GLB) is widely established by cloud providers, to exploit the differences in electricity price, local green energy generation, transmission delay and cost etc across geographically dispersed data centers (DCs). With GLB, a cloud provider can achieve reduction of electricity cost or/and bandwidth cost or/and delay cost. However, these objectives are not independent from the others. In this paper, we first build an offline optimization-based framework to explore the trade-off among these three objectives under an emerging practical scenario, where the DCs are charged by peak pricing and burstable billing for energy consumption and bandwidth usage, respectively. It turns out that minimizing a specified cost may result in remarkable increases of other costs. Then, we propose a short-term prediction based mechanism (SPM) for the cloud provider to periodically deduce the request distribution strategies. With real-world data traces, we show that SPM can always obtain a suitable trade-off among different costs.

Demand response is widely employed by today's data centers to response to the increasing of electricity cost. To incentivize users of data centers participate in the demand response programs, i.e., breaking the split incentive hurdle, some prior researches proposed market-based mechanisms such as dynamic pricing and static monetary rewards. However, these mechanisms are either intrusive or unfair. In this paper, we use time-varying rewards to incentivize users of data centers grant time-shifting of their requests. With a game-theoretic framework, we model/analyze the game between a single data center and its users. Further, we extend our design via integrating it with another emerging practical demand response strategies: server shutdown or local renewable energy generation. With real-world data traces, we show that a data center with our design can effectively shed its peak electricity load and overall electricity cost without reducing its profit, when compared with the current practice where no incentive mechanism is established.

Data centers spend millions of dollars on their electricity bills annually. Therefore, there is an interest among data center operators to control the electricity usage so as to minimize energy expenditure. However, when it comes to cloud data centers, the electricity usage is mainly controlled by the tenants. Yet, since most cloud data centers charge their tenants with flat rates, the tenants do not have incentives to change their electricity usage to contribute in cutting electricity bills by participation in demand response. Accordingly, in this paper, we propose a game-theoretic framework together with a time varying pricing (TVP) mechanism for cloud data centers to charge their tenants. In this approach, the TVP propagates the actual energy bill, which comprises both demand and energy charges, onto tenants' service costs. As an extension to this core idea, the time- varying amount of renewable energy generated by data center's on-site renewable generators is also taken into account to affect the payments. Our proposed pricing method is evaluated under various experimental data and simulations. We show that TVP can boost data center's profit by 8.2% and reduce the energy bill by 33.0% and improve tenants' aggregate surplus by 12.3%, when comparing it with a flat rates model that uses a widely employed billing method in today's cloud data centers.

Generally, data center's applications have different Quality of Service (QoS) requirements. Meanwhile, data center's tenants may give different priorities to performance and cost. Therefore, it is unsuitable to treat applications/tenants equally. In this paper, we adopt Dynamic Pricing (DP) to charge for the usage of bandwidth and provide tenants with capability to automatically response to the dynamic price. Further, for applications with tight delay requirements, we propose Dynamic Pricing with Bandwidth Reservation (DPBR), which can reserve bandwidth for specific applications. With the modelling of user satisfaction of cost and performance, we show that tenants with DP and DPBR can get better trade-offs between performance and cost. Comparing with Flat Pricing (FP), which is a representative of today's on-demand purchase option, we demonstrate that DPBR is a better option for tenants since it can maximize their satisfactions. The validity is demonstrated through numerical studies and simulations.

Data Center Traffic has the nature of diversity, variability and unpredictability. Due to the varying link state, the network bandwidth value changes. Traditionally, most of the t cloud providers employ static strategies based on predicting or pre-testing tenants' traffic characteristics [5] [8] [6]. Since no perfect traffic prediction methods have been proposed so far, these static methods result in unsatisfactory resource utilization and unreasonable cost. Therefore, this paper aims at designing a decentralized resource allocation method and a dynamic pricing policy based on network state and tenant demands. We can achieve work conservation and adaptability pricing with our network architecture. The simulation results show that DistributedNet can provide performance isolation, differentiated service and min-bandwidth guarantee.

With aggressive reductions in feature sizes and the integration of multiple functionalities on the same die, bottlenecks due to I/O pin limitations have become a critical issue in today's VLSI designs, especially for 3D IC technologies. To alleviate the pin limitation problem, a stacked-Vdd circuit paradigm has recently been proposed in the literature. However, for a circuit designed using this paradigm, a significant amount of power may be wasted if modules are not carefully assigned to different Vdd domains. In this article, we present a partition-based algorithm for efficiently assigning modules at the floorplanning level, so as to reuse currents between Vdd domains and minimize the power wasted during the operation of the circuit. Experimental results on both 3D and 2D ICs show that compared with assigning modules to different Vdd domains using enumeration and simulated annealing, our algorithm can generate circuits with competitive power and IR noise performance, while being orders of magnitude faster.

This paper addresses the module assignment problem in pinlimited designs under the stacked-Vdd circuit paradigm. A partition-based algorithm is presented for efficiently assigning modules at the floorplanning level so as to reuse currents between the Vdd domains, and minimize the power wasted during the operation of the circuit. Experimental results on a DLX architecture show that compared with assigning modules to different Vdd rails using a bin-packing technique, the circuit generated by our algorithm has 32% lower wasted power, on average. In addition, experiments on a 3D IC example show that our module assignment approach is equally effective in reducing the power waste in 3D ICs.

Due to technology scaling trends, the accurate and efficient calculations of the temperature distribution corresponding to a specific circuit layout and power density distribution will become indispensable in the design of high-performance very large scale integrated circuits. In this paper, we present three highly efficient thermal simulation algorithms for calculating the on-chip temperature distribution in a multilayered substrate structure. All three algorithms are based on the concept of the Green function and utilize the technique of discrete cosine transform. However, the application areas of the algorithms are different. The first algorithm is suitable for localized analysis in thermal problems, whereas the second algorithm targets full-chip temperature profiling. The third algorithm, which combines the advantages of the first two algorithms, can be used to perform thermal simulations where the accuracy requirement differs from place to place over the same chip. Experimental results show that all three algorithms can achieve relative errors of around 1% compared with that of a commercial computational fluid dynamic software package for thermal analysis, whereas their efficiencies are orders of magnitude higher than that of the direct application of the Green function method.

Fixed-die floorplanning is an important problem in the modern physical design process. An effective floorplanning algorithm is crucial to improving both the quality and the time-to-market of the design. In this paper, we present an analytical floorplanning algorithm that can be used to efficiently pack soft modules into a fixed die. The locations and sizing of the modules are simultaneously optimized so that a minimum total wire length is achieved. Experiments on the MCNC and GSRC benchmarks show that our algorithm can achieve above a 90% success rate with a 10% white space constraint in the fixed die, and the efficiency is much higher than that of the simulated annealing based algorithms for benchmarks containing a large number of modules.

With technology scaling, on-chip power densities are growing steadily, leading to the point where temperature has become an important consideration in the design of electrical circuits. This paper overviews several methods for the analysis and optimization of thermal effects in integrated circuits. Thermal analysis may be carried out efficiently through the use of finite difference methods, finite element methods, or Green function based methods, each of which provides different accuracy-computation tradeoffs, and the paper begins by surveying these. Next, we overview a restricted set of thermal optimization methods, specifically, placement techniques for thermal heat-spreading, and then we conclude by summarizing a set of future directions in electrothermal design.

3D integrated circuits (3D ICs) provide an attractive solution for improving circuit performance. Such solutions must be embedded in an electrothermally-conscious design methodology, since 3D ICs generate a significant amount of heat per unit volume. In this paper, we propose a temperature-aware 3D global routing algorithm with insertion of "thermal vias" and "thermal wires" to lower the effective thermal resistance of the material, thereby reducing chip temperature. Since thermal vias and thermal wires take up lateral routing space, our algorithm utilizes sensitivity analysis to judiciously allocate their usage, and iteratively resolve contention between routing and thermal vias and thermal wires. Experimental results show that our routing algorithm can effectively reduce the peak temperature and alleviate routing congestion.

Dramatic rises in the power consumption and integration density of contemporary systems-on-chip (SoCs) have led to the need for careful attention to chip-level thermal integrity. High temperatures or uneven temperature distributions may result not only in reliability issues, but also timing failures, due to the temperature-dependent nature of chip time-to-failure and delay, respectively. To resolve these issues, high-quality, accurate thermal modeling and analysis, and thermally oriented placement optimizations, are essential prior to tapeout. This paper first presents an overview of thermal modeling and simulation methods, such as finite-difference time domain, finite element, model reduction, random walk, and Green-function based algorithms, that are appropriate for use in placement algorithms. Next, two-dimensional and three-dimensional thermal-aware placement algorithms such as matrix-synthesis, simulated annealing, partition-driven, and force directed are presented. Finally, future trends and challenges are described

Temperature-related effects are critical in determining both the performance and reliability of VLSI circuits. Accurate and efficient estimation of the temperature distribution corresponding to a specific circuit layout is indispensable in physical design automation tools. In this paper, we propose a highly accurate fast algorithm for computing the on-chip temperature distribution due to power sources located on the top surface of the chip. The method is a combination of several computational techniques including the Green function method, the discrete cosine transform (DCT), and the table look-up technique. The high accuracy of the algorithm comes from the fully analytical nature of the Green function method, and the high efficiency is due to the application of the fast Fourier transform (FFT) technique to compute the DCT and later obtaining the temperature field for any power source distribution using the pre-calculated look-up table. Experimental results have demonstrated that our method has a relative error of below 1% compared with commercial computational fluid dynamic (CFD) softwares for thermal analysis, while the efficiency of our method is orders of magnitude higher than the direct application of the Green function method.

Thermal simulation has become increasingly important in chip design, especially in the nanometer regime, where the on-chip hot spots severely degrade the performance and reliability of the circuit and increase the leakage power. In this paper, we present a highly efficient and accurate thermal simulation algorithm that is capable of performing full-chip temperature calculations at the cell level. The algorithm is a combination of several important numerical techniques including the Green function method, the discrete cosine transform (DCT), and the frequency domain computations. Experimental results show that our algorithm can achieve orders of magnitude speedup compared with previous Green function based algorithms while maintaining the same accuracy.

The optimization of integrated spiral inductors has great practical importance. Previous optimization methods used in this field are either too slow or depend on very simplified assumptions in the device modeling which result in the algorithm only applicable to low-frequency cases. In this paper, we propose using the sequential quadratic programming (SQP) approach to optimize the on-chip spiral inductors. A physical model based on first principles is used in the back-end device-parameter extraction engine which makes the algorithm suitable to the optimization at any frequency range. In addition, compared with enumeration, which is used in many inductance optimization packages, our experiments show that the SQP algorithm can achieve at least an order of magnitude speedup while maintaining the same quality of the optimized design.