We describe a multiple reference and multiple block size motion estimation (ME) hardware design for professional encoder LSIs, that supports H.264/AVC High 4:2:2 profile, MPEG-2 4:2:2 profile and MPEG-4. An 8×8-based “telescopic” integer motion estimation (IME) followed by an “inclusive” variable block size fractional motion estimation (FME) results in a performance almost as good as the Joint Model (JM)’s exhaustive full search, while operation and control by two SIMD processors yield programmability and flexibility to motion search and mode decision methods. An encoder LSI with this architecture was successfully fabricated in a 90-nm CMOS process.

This paper proposes a new architecture for VASA, a single-chip MPEG-2 422P@HL CODEC LSI with multichip configuration for large scale processing beyond the HDTV level, and demonstrates its flexibility and usefulness. VASA is the world's first single-chip full-specs MPEG-2 422P@HL CODEC LSI with a multichip configuration. An LSI was successfully fabricated using the 0.13-mum eight-metal CMOS process. The architecture not only provides an MPEG-2 422P@HL CODEC but also large scale processing beyond the HDTV level for digital cinema and multiview/-angled live TV applications with a multichip configuration. The VASA implementations will lead to a new dimension in future high-quality, high-resolution digital multimedia entertainment.

This paper proposes a new architecture for a single-chip MPEG-2 video encoder with scalability for HDTV and demonstrates its flexibility and usefulness. The architecture based on three-layer cooperation provides flexible data-transfer that improves the encoder from the standpoints of versatility, scalability, and video quality. The LSI was successfully fabricated in a 0.25 /spl mu/m four-metal CMOS process. Its small size and its low power consumption make it ideal for a wide range of applications, such as DVD recorders, PC-card encoders and HDTV encoders.

This paper proposes a high-speed software-based platform for embedded software and evaluates its benefits on a commercial MPEG-2 video encoder LSI with HDTV scalability, The platform is written in C/C++ languages without any hardware description languages (HDLs) for high-speed simulation. This platform is applicable before writing up complete HDLs. The simulation speed is very fast and more than 600 times faster than compiled HDL simulators using RTL description. Fifty percent of the bugs in the final embedded software were located efficiently and quickly, and the design turn-around time was shortened by more than 25%. This platform provides sufficient performance and capability for validating practical embedded software.

This paper proposes a memory-based architecture implementing the MPEG2 system protocol large scale integrations (LSIs), and demonstrates its flexibility and performance. The memory-based architecture implements the full functionality of the MPEG2 system protocol for both multiplexing and demultiplexing MPEG2-encoded streams. It consists of a core central processing unit, memories, and dedicated application-specific hardware. It is designed and optimized by hardware/software codesign techniques. The LSI's provide sufficient performance and flexibility for real-time application of the MPEG2 system protocol. They were fabricated with 0.5 /spl mu/m CMOS embedded gate array process technology. They are now in use on MPEG2 codec systems for several multimedia communication and storage services.

An architecture and its four load balancing algorithms for a highly OR-parallel inference machine are proposed, and its performance is evaluated in a trace-driven simulation study. This inference machine consists of a large number of processing elements (PEs) with serial I/O links directly connected to each other in a simply modified mesh network. Each PE is a high-speed sequential Prolog processor with its own local memory. The activity of all PEs is locally controlled by four new load balancing algorithms based on purely local communication. Communication is allowed only between directly connected PEs. These load balancing algorithms reduce communication overhead in a load balancing and make it possible to accomplish highly OR-parallel execution. A software simulator using a trace-driven simulation technique based on an inference tree has been developed, and some typical OR-parallel benchmarks such as the n-queens problem have been simulated on it. The average communication per load balancing is reduced by a factor ranging from 1/30 to 1/100 by the interaction of these load balancing algorithms as compared with a conventional copying method. The inference machine (1024 PEs; 32/spl times/32 array) attains 300-600 times parallel speedup, assuming 1 MLIPS (mega logical inferences per second) PE and a 20 MBPS (mega bits per second) each serial I/O link, which could be easily integrated on a single chip using current VLSI technology. This highly OR-parallel inference machine promises to be an important step towards the realization of a high-performance artificial intelligence system.>

A content addressable memory (CAM)-based machine architecture is proposed for a high-speed Prolog machine. This Prolog machine attempts to speed up the total Prolog execution performance by using a hierarchical pipelined scheme and a CAM-based backtracking scheme. The hierarchical pipelined scheme reduces the total number of Prolog execution steps to half of that using the conventional method. The CAM-based backtracking is efficiently and quickly achieved by using CAM's sophisticated garbage collection function, which eliminates the need for stacks and additional operation cycles. In this machine, all Prolog execution can be simply controlled by a semantic information 'inference depth' without any address handling by storing all working information, binding and control information, in CAMs. This machine attains a performance of 100 KLIPS (kilo logical inference per second) on the deterministic append program in the interpretive mode, and also attains high performance in the nondeterministic program.>