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Shih-Min Shu

dblp:15/2408 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2004
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 50% Processor architecture and microarchitecture · 25% Integrated circuit design · 25%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
digital circuit design
0.012004
Pipelining Sequential Circuits with Wave Steering · IEEE Trans. Computers 2004
Electronic design automation › logic synthesis
finite state machine synthesis
0.012004
Pipelining Sequential Circuits with Wave Steering · IEEE Trans. Computers 2004
Electronic design automation
high-level synthesis
0.012004
Pipelining Sequential Circuits with Wave Steering · IEEE Trans. Computers 2004
Processor architecture and microarchitecture
pipelining
0.012004
Pipelining Sequential Circuits with Wave Steering · IEEE Trans. Computers 2004

Methods — techniques the papers use, named apart from their topics

wave steering · 0.0FSM decomposition · 0.0
YearPublicationVenuePosition
2004 Pipelining Sequential Circuits with Wave Steering
abstract
We address the problem of designing very high-throughput finite-state machines (FSMs). The presence of loops in sequential circuits prevents a straightforward application of pipelining to increase performance. We observe that appropriate extensions of the "wave steering" technique can partially overcome the problem. We find that FSM decomposition theory is useful for decoupling the state-variable dependencies. Experiments on MCNC benchmarks show a 217 percent improvement in throughput, at the expense of a similar increase in area (2.15 times). Latency loss is relatively small, on the order of 20 percent, as compared to standard cell implementations.
Luca Macchiarulo, Shih-Min Shu, Malgorzata Marek-Sadowska
IEEE Trans. Computers2