This article presents a systematic approach to generate layouts for two devices, with an arbitrary integer ratio of device sizes, that cancels up to at least third-order gradient effects. A new analysis leads to mathematical constraints on 1-D layouts that meet the required integer ratio and cancel second-order gradients. From those layouts, we apply reflection and rotation symmetries to generate 2-D layouts that cancel higher-order gradients. We demonstrate our proposed methodology on current sense transistors interspersed in active power transistors. Legato electrothermal simulation show our proposed approach, respectively, improves worst-case matching accuracy about a factor of 9.9 and 7.15 when compared to a common centroid (CC) and interdigitated (ID) pattern in the presence of gradients effects. Furthermore, we discuss evaluation metrics that can be used to select one of multiple gradient canceling layouts for any fixed rectangular grid and device application.

This article presents two improvements to, and a warning about a previously unrecognized issue with, statistical modeling, characterization, and simulation. We focus on mismatch, which is key for analog IC design, but the topics addressed are generic. For relative variation (i.e., % difference), we show that conventional measures have significant issues when the variation is large. We present two new measures of % difference between$y_{2}$and$y_{1}$and show that$100 \cdot {\mathrm {ln}} (y_{2} / y_{1})$is the only measure that is physically correct for mismatch. We review existing, but not widely known, robust alternatives to the textbook approach to estimate standard deviation, show the limitations of these, and propose a new method that is intermediate between, and overcomes limitations of, the textbook and robust approaches. We then show how the accuracy of mismatch simulation, critical for analog IC design, is affected by “spurious correlation” between statistical samples; we are not aware that the importance of this has been recognized previously.

This article shows how to properly define modulated flicker noise in Verilog-A compact models, and how a simulator should handle flicker noise for periodic and transient analyses. By considering flicker noise in a simple linear resistor driven by a sinusoidal source, we demonstrate that the absolute value formulation used in most existing Verilog-A flicker noise models is incorrect when the bias applied to the resistor changes sign. Our new method for definition overcomes this problem, in the resistor as well as more sophisticated devices. The generalization of our approach should be adopted for flicker noise, replacing the formulation in existing Verilog-A device models, and it should be used in all new models. Since Verilog-A is the de facto standard language for compact modeling, it is critical that model developers use the correct formulation.

This paper presents criteria, using simple integer arithmetic, to determine if a layout of a pair of devices broken into multiple, identical sections cancels the effect of nonlinear process gradients. These criteria allow quantification of 12 layout symmetries that can be leveraged to cancel specific process gradient components. “Dispersion,” the degree to which device segments are distributed throughout a layout, is also quantified in a simple and intuitive way, and used to identify which of multiple gradient canceling layouts is best. Techniques to construct maximally dispersive quadratic gradient canceling layouts with arbitrary numbers of rows and columns are presented.

PSP and the backward propagation of variance (BPV) method are used to characterize the statistical variations of metal-oxide-semiconductor field effect transistors (MOSFETs). BPV statistical modeling of NMOS and PMOS devices is, for the first time, coupled by including self-consistent modeling of ring oscillator gate delays. Parasitic capacitances are included in the analysis. The proposed technique is validated using Monte-Carlo simulations and by comparison to experimental data from two technologies.

Accurate statistical modeling and simulation are keys to ensure that integrated circuits (ICs) meet the specifications over the stochastic variations that are inherent in IC manufacturing technologies. Backward propagation of variance (BPV) is a general technique for statistical modeling of semiconductor devices. However, the BPV approach assumes that statistical fluctuations are not large so that variations in device electrical performances can be modeled as linear functions of process parameters. With technology scaling, device performance variability over manufacturing variations becomes nonlinear. In this paper, we extend the BPV technique to take into account these nonlinearities. We present the theory behind the technique and apply it to specific examples. We also investigate the effectiveness of several possible solution algorithms.

In the above titled paper (ibid., vol. 28, no. 9, pp. 1428-1432, Sep. 09), there was a typo in (1), and (10) and (11) were incorrect of there is more than one forward propagation of variance (FPV) variable. The correct expressions for these three equations are presented here.

Compact MOSFET models are a critical link between technology and design. The inexorable reduction in supply voltage and geometry to 45nm and below adds or emphasizes physical effects not important in the past, and so continues to expand the requirements for MOSFET models. At and below 45nm, process variations, reliability, proximity effects, high-k gate materials, and non-classical device structures all challenge modeling. This tutorial presents fundamentals and evolution of compact MOSFET models, and techniques to address the new challenges.

The p-n junction depletion capacitance models of the SPICE and ADVICE circuit simulators are regional models that have discontinuities in high-order derivatives. This limits the order of integration that can be used for transient analyses, and can limit both the size of time steps that can be used during transient analyses and the accuracy of distortion analyses. In addition, the SPICE and ADVICE depletion capacitance models unphysically predict that the depletion charge increases without bound as applied forward bias increases. An improved depletion capacitance model that overcomes these problems is presented. The model is charge-based, single-piece, and C/sub infinity /-continuous, and has a finite maximum junction depletion charge under forward bias.>