The settling-time in single-pole operational transconductance amplifiers (OTAs) is analyzed including the effect of slew-rate limitations. A useful design equation is provided and extended to three-pole OTAs. A design procedure is carried out and validated through simulations.

In this paper we are going to analyze the settling-time in single-, two- and three-stage amplifiers with the intent of deriving approximate but useful design equations that include the effects of the zeros and of the slew-rate limitations. The analysis is mainly devoted to the definition of an approach for the design of three-stage CMOS operational transconductance amplifiers from settling-time specifications. A design example is carried out to validate the proposed approach.

In this communication, we propose a new non-inverting class-AB CMOS output stage suitable for driving high-capacitive loads in three-stage amplifiers that make use of the Reversed Nested Miller technique for the frequency compensation. The output stage is verified through the design of a three-stage OTA suitable for driving a 500-pF capacitive load in a 65-nm CMOS process. The goodness of the proposed output stage is verified in the Cadence environment.

In this communication we propose a simple and well-defined approach for the design of fast settling amplifiers suitable for switched capacitors circuits. The design is based on a settling-time oriented compensation that makes the phase of the closed-loop amplifier to be linearly related to the frequency, thus emulating the behavior of an ideal delay, like in a Bessel filter. The design and the simulation of a three-stage amplifier in a 65-nm CMOS process validate the proposed settling-time oriented approach.

The Silicon Photomultiplier (SiPM) is a promising kind of device able to detect single photons thus permitting the measurement of weak optical signals. The design of high-performance front-end electronics for the read-out, require an accurate model of the SiPM. In this paper we propose a new SiPM model implemented through the behavioral language Verilog-a and suitable for transistor-level circuit simulation. The model is based on a traditional electrical model and a statistical modeling to implement the SiPM noise characteristic in terms of dark-count and after-pulsing phenomena. We also provide a procedure for extracting the model parameters from measurements and validate both the extraction procedure and the Verilog-a model by comparing simulations to measurement results.

In this communication, an ultra-compact I-V nanometer MOS model is used to predict the dynamic characteristics (propagation delay and rise/fall times) of CMOS inverter and more complex stacked-transistor gates. Simulations reveal typical errors within 1-3% (always less than 6%) for the simple inverter case and within 4-8% (always less than 11%) in the case of stacked-transistor gates.

An accurate behavioral model for simulating Single-Photon Avalanche Diodes (SPADs) is introduced. The device operation is described using the Verilog-A description language. The derived model is able to emulate the static, the dynamic behavior and the main statistical effects of a SPAD, such as the turn-off probability, the dark-count and the after-pulsing phenomena. Spectre simulations reveal the validity of the approach.

In this communication, we propose a Miller compensation technique for low voltage LDO regulators which makes use of a current amplifier. The analysis shows how to design the compensation network when no voltage buffer is placed between the LDO error amplifier and power device and suggests a low supply voltage circuit topology that allows to compensate with a reasonably low integrated capacitance, to avoid oscillations due to the complex-conjugate poles at high output currents and to obtain acceptable under/overshoots during fast transient load variations. The designed LDO regulator can work with a supply voltage down to 1.2 V with a drop-out voltage of 200 mV at maximum load current of 100 mA; the integrated compensation capacitance is 25 pF, the load capacitor being equal to 1 muF. Simulations in good agreement with the theoretical results are also shown.

We propose a representation and a related methodology for evaluating the exact input and output resistances of feedback amplifiers. The approach is based on the generalization of the Rosenstark theorem. Indeed, it requires the computation of two resistances (direct and asymptotic) each one evaluated in one of the two ideal and extreme conditions of the return ratio (zero or infinity). Due to these characteristics, the representation allows one to understand what happens to a feedback amplifier resistance in the case of absence of feedback or in the ideal case of infinite feedback.

The transient response of a feedback two-stage OTA is analyzed in terms of slew-rate and gain-bandwidth product. An expression for the settling time is carried out. The results are then used to propose a design procedure for the two-stage OTA. The procedure is based on "settling time constraint" and on the use of the gm-over-IDratio so to maximize the nodes voltage swing. The theory is validated by means of simulations and so is done for the design procedure.

Bandgap voltage references are almost ubiquitous in CMOS systems. In many applications it is therefore extremely important to evaluate their robustness against power supply disturbances, which may be quantified by the power supply gain (PSG). Here we analyze the PSG of a very popular CMOS bandgap circuit topology; two design strategies are compared and simple, accurate models are provided

This paper presents a general architecture for an analog-to-digital (A/D) fuzzy converter which performs the A/D conversion and the fuzzification operation on the same functional block, through a programmable membership function. The solution uses as main blocks an A/D converter, a comparator, and some logic inverters and switches. It is characterized by good flexibility and programmability and, compared to conventional approaches, allows a significant amount of silicon area to be saved. The architecture proposed does not depend on the specific A/D converter adopted. However, low-voltage operation and reduced power dissipation as well as full compatibility with digital technologies can be achieved through the use of current-mode design techniques. A CMOS implementation is then proposed and nonidealities, limiting the resolution, are analytically evaluated in detail. Simulations based on a 0.35-/spl mu/m standard technology, which are in excellent agreement with the theoretical results, are also given.

A CMOS voltage to current converter is proposed which is based on a cross-coupled class AB topology. Thanks to its high-linearity and high-frequency performance, the circuit can be used in high-frequency applications such as mixers, IF amplifiers and filters, etc., where linearity is one of the most critical performance parameters. When the proposed circuit is compared with other voltage to current converters such as the source-coupled pair a much higher linearity is achieved at the same power consumption.

A new Switched Capacitor Membership Function circuit, which is based on an offset insensitive SC amplifier and presents triangular-shape transcharacteristics, is proposed. Thanks to the SC approach a good precision, which is independent of process tolerances, is achieved. The circuit was realised in a 1.2-/spl mu/m standard CMOS technology and both simulations and experimental data were carried out. Good agreement is shown between expected and measured values.

New and simple CMOS mixer powered with 1.5 V is presented. It works with a 200 MHz clock, and has a -7-dB IP/sub 3/. Moreover, it elaborates signals up to 150 mV with 1-dB compression point. The particular topology makes it useful for an integration in fully digital ICs.