This article proposes a novel graph recurrent neural network (GRNN)-based approach for detecting the eavesdropping attacks in smart grid wireless communication systems enabled by simultaneous wireless information and power transfer (SWIPT). By leveraging the graph-centric nature of GRNNs, the proposed method effectively learns the topological structure and the edge features of the wireless sensor networks (WSNs), enabling the detection of the eavesdropping attacks in dynamic WSNs. This article mathematically models the channel state information (CSI) under the man-in-the-middle eavesdropping attacks based on the physical-layer security (PLS) in SWIPT networks. Moreover, this article sets up a real-world testbed to create the training and testing data sets. The proposed GRNN model can handle large-scale complex topologies and dynamic eavesdropping networks, accurately detect eavesdropping behaviors, and enhance the security of information transmission in WSNs. Simulation results demonstrate that, compared with the algorithms, such as support vector machine (SVM), K-nearest neighbors (KNNs), convolutional neural network (CNN), graph convolutional network (GCN), and gated recurrent unit (GRU), the proposed method exhibits stronger robustness under complex attack scenarios, achieving a detection accuracy of over 95%. This article provides a novel and effective graph learning solution for the smart grid wireless communication security, which is of great significance to ensure the stable and reliable operation of the smart grids.

Long design cycles due to the inability to predict silicon realities are a well-known problem that plagues analog/RF integrated circuit product development. As this problem worsens for nanoscale IC technologies, the high cost of design and multiple manufacturing spins causes fewer products to have the volume required to support full-custom implementation. Design reuse and analog synthesis make analog/RF design more affordable; however, the increasing process variability and lack of modeling accuracy remain extremely challenging for nanoscale analog/RF design. We propose a regular analog/RF IC using metal-mask configurability design methodology Optimization with Recourse of Analog Circuits including Layout Extraction (ORACLE), which is a combination of reuse and shared-use by formulating the synthesis problem as an optimization with recourse problem. Using a two-stage geometric programming with recourse approach, ORACLE solves for both the globally optimal shared and application-specific variables. Furthermore, robust optimization is proposed to treat the design with variability problem, further enhancing the ORACLE methodology by providing yield bound for each configuration of regular designs. The statistical variations of the process parameters are captured by a confidence ellipsoid. We demonstrate ORACLE for regular Low Noise Amplifier designs using metal-mask configurability, where a range of applications share common underlying structure and application-specific customization is performed using the metal-mask layers. Two RF oscillator design examples are shown to achieve robust designs with guaranteed yield bound.

As the design-manufacturing interface becomes increasingly complicated with IC technology scaling, the corresponding process variability poses great challenges for nanoscale analog/RF design. Design optimization based on the enumeration of process corners has been widely used , but can suffer from inefficiency and overdesign. In this paper we propose to formulate the analog and RF design with variability problem as a special type of robust optimization problem, namely robust geometric programming. The statistical variations in both the process parameters and design variables are captured by a pre-specified confidence ellipsoid. Using such optimization with ellipsoidal uncertainy approach, robust design can be obtained with guaranteed yield bound and lower design cost, and most importantly, the problem size grows linearly with number of uncertain parameters. Numerical examples demonstrate the efficiency and reveal the trade-off between the design cost versus the yield requirement. We will also demonstrate significant improvement in the design cost using this approach compared with corner-enumeration optimization.